IEEE double extended forma

[David G. Hough on validgh]

> The IEEE standard 754 does not specify an exact format for double extended
> but only gives some minimum requirements.  It appears to me that a de facto
> standard has emerged:
>  
>     1 bit for the sign
>    15 bits for the exponent
>   112 bits for the fraction
>   ---
>   128 bits total
>     1 implicit bit, so 113 bits for the significand
>  
>       exponent bias of +16383

This is the "quad" format specified in the SPARC and PA-RISC instruction
set architectures, and possibly others.   It hasn't been implemented in 
hardware yet.    It could be used in lieu of conventional x86 or 68k extended
for many purposes, if fast enough, but is really intended to solve bigger
problems than those could.

> Another proposal can be found in the draft proposal IEEE P.1596.5/D0.95 "Shared
> Data Formats optimized for Scalable Coherent Interface Processors". In there,
> there is a "floating hexlet":
>  
>   1 sign
>  23 exponent
> 104 mantissa
> ---
> 128 total
>   1 implicit bit, so 105 bits for the significand
>  
> exponent bias of +4194303
>  
> Any ideas on what name to call this in "C"?

"A mistake!"   I don't know any benefit to having such a large exponent 
range.   It merely postpones the moment of reckoning when a wildly divergent
computation finally starts to produce exceptions.

The most significant alternative to either SPARC/PARISC quad or
x86/68k extended is "doubled precision" quad from RS/6000 or PowerPC.
Two doubles are used to represent quadruple precision with no increase in
exponent range.   The only merit in this approach is that it is relatively
cheap in software if fused multiply-add is available in double precision.