[Numeric-interest] Intel architecture question

[Douglas Priest]

The November 2006 version of the "Intel 64 and IA-32 Architecture
Software Developer's Manual" says that the SSE instructions

cvtpi2ps, cvtps2pi, cvttps2pi, cvtpi2pd, cvtpd2pi, and cvttpd2pi

act like MMX instructions in that they (a) set the x87 tag word
to indicate that all x87 fp stack registers are valid and (b) set
the x87 stack top pointer to zero.  (The manual mentions that the
cvtpi2pd instruction only does this when the operand is in an MMX
register and not when the operand is in memory.  Apparently the
same is true for cvtpi2ps.)

It looks to me as though when one of these instructions raises an
unmasked numeric exception, the x87 tag word and stack top pointer
are modified _before_ a trap is taken even though the general rule
for SSE instructions is that they do not modify any state (other
than the exception flags in the MXCSR) when unmasked exceptions
occur.  I haven't found any documentation to support my observation.
Can someone on this list confirm it?

Thanks,
Doug Priest