double rounding in x86

[uunet!F.GP.CS.CMU.EDU!Jonathan_R_Shewchuk]

Tom Lynch described one of the difficulties of storing extended-precision
floating-point registers to double-precision values in memory:

>      A small value rounds to a value half way between two representable
>      values in the reduced exponent range.  A store is done, hence
>      a second rounding.  Double rounding of a result is certainly not
>      IEEE 754 compliant.

One interesting aspect of this case is that one can imagine designing a
processor in which each internal extended-precision register has two
accompanying tag bits that specify whether the register value has been
rounded up, has been rounded down, or is exact.  These tag bits could be
used during storage to ensure that the value is rounded as it would have
been if the result of the original computation had been rounded directly to
double-precision; hence double rounding is avoided.  I wonder if any existing
hardware does this?  I wonder if this idea is actually forbidden by IEEE
754/854 because the second rounding is technically nonconformant?

While we've seen discussion over the past few days regarding whether double
rounding is IEEE 754 compliant, there's been little mention of how harmful
double rounding might be to applications.  For my own part, I work on
algorithms for simulating arbitrary-precision floating-point arithmetic
(refinements of algorithms of Doug Priest).  I have some nice fast algorithms
with exceedingly tricky correctness proofs, and I don't believe the algorithms
will work in the presence of double rounding (though the pathological cases
will probably be quite rare).  I'd like to hear of any other algorithms for
which double rounding is a serious threat.  It seems to me that such algorithms
are as strong an argument against hardware that double rounds as the fine
print of the IEEE documents.

Jonathan Shewchuk
School of Computer Science
Carnegie Mellon University
jrsacs.cmu.edu