IEEE double extended format

[Joel Boney]

| From huckansa.hp.com Mon Feb  1 13:03:49 1993
| From: Jerry Huck <huckansa.hp.com>
| Subject: Re: IEEE double extended format
| 
| > The IEEE standard 754 does not specify an exact format for double extended
| > but only gives some minimum requirements.  It appears to me that a de facto
| > standard has emerged:
| > 
| >     1 bit for the sign
| >    15 bits for the exponent
| >   112 bits for the fraction
| >   ---
| >   128 bits total
| >     1 implicit bit, so 113 bits for the significand
| > 
| >       exponent bias of +16383
| > 
| > My questions are:
| > 
| > 1)  Do you think that this is the appropriate format for double extended?

Actually there are 2 "defacto" standards for "extended". One was used on the
M68881/2 and 80387 type hardware and is 80 bits and encoded as:

	1 bit for sign
       15 bits for exponent
       64 bits for the fraction

The other defacto standard is the one you listed.

| 
| Yes.  The latest architecture manual (part #09740-90039) on PA-RISC
| uses this same format. 

The SPARC Version 8 (32-bit) and SPARC Version 9 (64-bit) architectures
use the same  format too. We also call it quad. 


... stuff deleted

| 
| Jerry Huck  (huckansa.hp.com)
| Computer System Architecture
| Hewlett-Packard
| 
| 

				-- joel boney
				   HaL Computer
				   Vice Chair SPARC Architecture Committee