another volley in the RISC chip wars, delete if not interested
David Hough
sun!Eng!David.Hough
Thu May 7 17:14:27 PDT 1992
The following has been officially filtered by TI and SMCC.
I can't comment on any missing information, but I know some people will be
able to glean some useful data from the press release.
The fact that there are no unfinished fpops means, for instance, that
gradual underflow is just as fast as abrupt underflow.
Date: Thu, 7 May 92 15:55:33 PDT
TEXAS INSTRUMENTS ANNOUNCES AVAILABILITY OF SuperSPARC(TM),
INDUSTRY'S MOST HIGHLY INTEGRATED RISC MICROPROCESSOR
HOUSTON (May 7, 1992) -- The industry's most highly integrated
reduced instruction set computing (RISC) microprocessor is being
produced by Texas Instruments, the company announced today. The
superscalar microprocessor is designed to simplify the development
of multiprocessing systems from high-volume desktop applications to
powerful, massively parallel systems. Thousands of existing SPARC(TM)
software applications are compatible with this single chip
microprocessor.
Co-developed with industry leading workstation manufacturer Sun
Microsystems Computer Corporation, the 3.1 million transistor
SuperSPARC microprocessor delivers peak performance of 150 million
instructions per second (MIPS) at 50 MHz. Through on-chip support
for MBus, an industry-standard module bus, up to four SuperSPARC
microprocessors can be combined to deliver a peak performance of 600
MIPS. Up to 64 SuperSPARC microprocessors can be connected in
parallel through XBus, a packet-switched extension bus.
The key to SuperSPARC's usability in a wide range of system
configurations is its high level of feature integration, including
a superscalar "engine" that executes up to three instructions in
each clock cycle. This "engine", combined with the largest on-chip
caches available on any RISC processor today and an IEEE-compatible
floating-point unit, provides high performance in a single chip.
"SuperSPARC's superior ability to handle multiple instructions in a
single clock cycle makes it a winner for high performance commercial
multiprocessor systems," said Andrew Roberts, managing director, Mid
Range Systems Division, ICL PLC. "Its high level of integration
makes it an ideal general-purpose processor, suited for a wide range
of applications ranging from technical workstations to large
distributed transaction processing systems."
SuperSPARC FIRST TO MAKE RISC MULTIPROCESSING EASY
SuperSPARC is the first single-chip SPARC microprocessor to have
complete built-in multiprocessing. SuperSPARC multiprocessing
allows system vendors to expand from one to many microprocessors in
the same system by using plug-compatible modules to scale
performance. Computers from desktop workstations to massively
parallel supercomputers can utilize differing quantities of the same
modules to attain required performance.
"With MBus SuperSPARC modules, users have an easy means of upgrading
systems as the performance of microprocessors increases," said Dave
Ditzel, director of advanced development at Sun Microsystems
Laboratories Inc. "This saves existing investments in surrounding
memory, disks, peripherals and software applications."
System-ready modules from TI include a SuperSPARC MBus module
running at 33 MHz and 40 MHz and a SuperSPARC MultiCache module
running at 33 MHz, 40 MHz, 45 MHz and 50 Mhz. The SuperSPARC
MultiCache module will include the SuperSPARC MultiCache Controller,
an optional bus/cache controller and 1-MByte of expansion cache
using industry 128K x 9 synchronous static random access memories
(SRAMs). The SuperSPARC MultiCache module offers premium
performance when used with the packet-switched XBus (extension bus)
developed for large-scale multiprocessing by Xerox Palo Alto
Research Center (PARC). Both MBus and XBus operate asynchronously
from the SuperSPARC microprocessor, allowing CPU speed to scale
independently from the bus speed.
SPARC ARCHITECTURE COMPATIBILITY
The SuperSPARC microprocessor is a fourth-generation, superscalar
implementation of the SPARC architecture and is completely SPARC
binary compatible, supporting thousands of existing SPARC
applications. It complies with Version 8 of the SPARC Architecture,
published by SPARC International, preserving end user investment in
SPARC applications software. Due to the superscalar architecture,
SuperSPARC-based systems will offer an immediate performance gain of
up to three times conventional architectures for close to 5,000
applications spanning financial management, publications,
engineering, manufacturing and business environments. Popular
commercial titles include Lotus 1-2-3 and WordPerfect.
IDC reports that the SPARC architecture is the most widely accepted
RISC architecture, accounting for 63.1% of the RISC market in 1991.
It is supported by more than 11 semiconductor companies, fifty plus
systems companies and thousands of applications software and
operating systems vendors, fostering an environment conducive to
continued developments in microprocessors, software and systems.
"SuperSPARC is yet another example of the scalability and
flexibility of the SPARC architecture," said Bob Duncan, chairman of
SPARC International. "It is an important milestone for an
architecture that will continue to lead the industry through the
next decade."
SUPERSPARC DESIGNED FOR VOLUME
SuperSPARC's superscalar architecture achieves high performance
while avoiding complex systems engineering inherent with very high
clock rates. Higher clock rates translate into the need for more
specialized engineering and more expensive parts which can
dramatically affect system vendors' ability to deliver volume.
"The goal of our program was to achieve performance through
superscalar parallelism and multiprocessing as opposed to depending
on clock rates over 100 MHz, which make system design more difficult,"
said Steve Krueger, senior member technical staff at TI. "In balancing
the needs of software applications and system design, we developed a
superscalar, multiprocessing chip which lets the OEM and end-user
pick the system performance needed, while allowing for easy
upgradeability if performance needs increase."
SuperSPARC AVAILABILITY
TI is in volume production of SuperSPARC now and taking orders from
key SPARC International Executive Members for 33 and 40 MHz
configurations, with 45 and 50 MHz configurations to follow later
this year. TI will begin accepting orders from non-executive
members during the third quarter of 1992, with delivery in the
fourth quarter.
For system houses wanting to design SuperSPARC-based systems, a
SuperSPARC System Design Starter Kit -- including advanced system
development tools, documentation, technical support and several
SuperSPARC units -- is available from TI at $50,000, with expected
availability in the third quarter 1992.
SuperSPARC, TMS390Z50, and the optional SuperSPARC MultiCache
Controller, TMS390Z55, are fabricated using TI's EPICTM IIB
0.8-micron, triple-level metal BiCMOS process. This process
provides the density and performance enablers that make a
microprocessor with greater than three million transistors possible.
1988 COOPERATIVE AGREEMENT SET THE STAGE FOR SuperSPARC DEVELOPMENT
The strategic relationship that developed SuperSPARC was established
in late 1988, when TI and Sun signed a long-term cooperative
development agreement to advance SPARC state-of-the art. The Sun/TI
SuperSPARC team focused on leveraging Sun's sophisticated systems
design and architecture expertise and TI's VLSI process technology
and high-volume manufacturing capabilities. The SuperSPARC
development team includes TI and Sun members at sites in Texas and
California, working closely throughout all phases of the SuperSPARC
program.
------------------------------------------------------------------
Fact Sheet
The SuperSPARC Microprocessor
4/92
TEXAS INSTRUMENTS SUPERSPARC (TM) TMS390Z50 MICROPROCESSOR
Key Features Integrated on Chip
O SPARC Compatible
- Runs old SPARC binaries and binaries compiles for SuperSPARC
pipeline
- Industry's only openly evolved architecture
- Multiprocessing memory model (total store ordering and
partial store ordering)
O Flexible Superscalar Engine: Integer Unit Control, Superscalar
Integer Execution
- Executes up to three instructions per clock cycle
- Abundant execution units for flexible scheduling of
instructions
- Fixed pipeline: Instructions move in groups through the
pipeline
- Unique arrangement of cascaded 32-bit ALUs (arithmetic logic
units) for executing multiple integer instructions in the
same clock
- SPARC compatibility - dynamically groups and schedules
instructions in hardware without the help of compilers.
- Four instruction per cycle fetch, eight instruction prefetch
queue, four instruction branch target queue
- Low branch latency, handles most taken and untaken branches
without pipeline stalls.
- Single cycle, 64-bit loads and stores with no load-use
penalty
O High performance per MHz
- 50 MHz cycle time scalable to 100 MHz over time
- Four-way multiprocessing with a peak instruction execution of
600 million operations per second (MIPS) scalable to 1200
MIPs over time
- Uniprocessing with a peak instruction execution of 150 MIPS
scalable to 300 MIPS over time
O High-Performance SPARC Floating-Point Unit
- Complete single- and double-precision IEEE floating-point
math
- No unfinished operations
- Tightly linked to integer pipeline, excellent performance
balance
- Integer multiply and divide
O Largest On-Chip Caches of any RISC Microprocessor
- Faster execution of real-world application software
- 20-Kbyte instruction cache: 128-bit wide access, 5-way set
associative, physically addressed, 32-byte sub-block, 64-byte
lines, burst fill prefetch
- 16-Kbyte data cache: 64-bit wide access, 4-way set
associative, physically addressed, 32-byte sub-block, write
back (no external cache), write through (external cache)
O SPARC Reference MMU (memory management unit)
- 64 entry, fully associative TLB
- Hardware reload
O Complete multiprocessing on-chip
- MBus (multiprocessing bus) Level II fully synchronous chip-
to-chip multiprocessor bus, coherent protocol, 64-bit wide
datapath, snoop logic
- Store/copyback buffer
O SuperSPARC bus to external bus/cache controller (deselected if
MBus mode)
O System Support Features
- Data and instruction prefetch for improved cache performance
- Support for partial store ordering
- Instruction or cycle counter
- Phase locked loop for clock skew control
O Extensive test/debug support
- Built-in-self test
- JTAG scan-based emulation
- ICE-like debugging features
O Packaging
- High performance dense CPGA (ceramic pin grid array) with
heatsink
O Physical Characteristics
- 3.1 million transistors
- TI's 0.8 micron EPIC IIB triple metal BiCMOS process
- Dense CMOS core with bipolar I/O and interconnect
- Die size: 15.98 mm x 15.98 mm
- Power supply: 5V +/- 5%
- Power dissipation: 8 watts typical
Companion SuperSPARC MultiCache Controller
O Supports high performance uni- and multiprocessor systems
- Cache tags and cache control for 1-MByte of external cache
(MBus) or 512-KByte, 1-MByte or 2- MByte (XBus)
- Built-in support for multiprocessing cache coherence
- Highest SuperSPARC performance
O Selectable System Bus Interface
- Direct connect to industry-standard MBus
- Packet interface supports other multiprocessing buses
O Separate Bus and Processor Clocks
- Processor may be operated at higher clock rates than the
system bus
- Allows simple performance upgrades
O Test and Debug support
- Built-in self test
- JTAG (IEEE 1149.1) boundary scan and test
O Other System Features
- Efficient memory block copy and block initialize functions
utilize system bus block transfers
- 8-bit local peripheral bus (XBus only)
- Data prefetching
- Event counters allow cache performance to be monitored
O Same EPIC IIB BiCMOS process as the SuperSPARC Microprocessor
O 369 pin CPGA package
------------------------------------------------------------------
TI TO FOLLOW SUPERSPARC WITH NEXT-GENERATION CPU PRODUCTS
BASED ON SMCC'S SPARC SILICON DESIGNS
Ongoing Relationship Will Benefit System Developers
HOUSTON, (May 7, 1992) -- The SuperSPARC(TM) microprocessor introduced today
by Texas Instruments (TI) is the first in a series of products from TI that
will utilize designs from Sun Microsystems Computer Corp. (SMCC). Spanning
a wide range of prices and performance levels, these future microprocessor
products will be available to system manufacturers worldwide.
SPARC microprocessors resulting from the TI/SMCC collaboration will reflect
the evolving architecture as defined by SPARC International, Inc. As part
of their continuing relationship, TI and SMCC are already developing a
family of highly integrated SPARC microprocessors that will accelerate
SPARC's penetration into the low-cost desktop, portable and embedded
markets. The first microprocessor to be available in the new family is
currently being developed under a project codenamed Tsunami. It is a
low-power "workstation on a chip" that will make possible the creation of
very low-cost SPARC workstations with outstanding performance.
Also under development is a very high-performance, next-generation series of
processors that will extend the SuperSPARC family. These high-end
SuperSPARC follow-ons will utilize the most advanced semiconductor
technologies, such as 64-bit architectures and will function as single-chip
supercomputing engines.
According to the two companies, by the year 2000, their new SPARC
microprocessors could contain more than 100 million transistors, operate at
clock rates approaching one billion cycles per second and deliver
performance exceeding two billion instructions per second.
Both product lines will incorporate TI's leading-edge semiconductor process
technologies, from the 0.8-micron EPIC IIB BiCMOS process used in today's
SuperSPARC, to 0.1-micron CMOS and BiCMOS processes planned for the future.
These chips will also use TI's advanced packaging technologies, including
multichip module (MCM) and fine pitch tape automated bonding (TAB) packaging
to manage performance increases and reduce system footprints.
Besides leveraging TI's processing and packaging strengths, this ongoing
collaboration between SMCC and TI makes use of SMCC's expertise in silicon
design. The relationship between the two companies is also an example of
the silicon design program recently made public by SMCC under which its
designs are licensed to semiconductor vendors, who manufacture, sell and
support the resulting chip products. One objective of the program is making
products from semiconductor vendors available early rather than after SMCC
systems containing these products are introduced and shipped.
------------------------------------------------------------------
SMCC SuperSPARC Q&A
SUPERSPARC STATUS
Q1. What is the SuperSPARC availability status?
A. SuperSPARC is in production for key members of SPARC
International. TI has determined that during volume ramp-up, they
will focus on SI Executive members as their initial customers. During
initial product release, this will allow them to focus support
resources, etc. on a manageable set of customers. TI will be making
SuperSPARC available to any interested parties. General market availability
is targeted for calendar Q4 1992, with a Design Starter Kit available to
the general market in Q3. SMCC is not inhibiting the availability of
SuperSPARC. TI has selected this priority strategy to optimize production
ramp and support abilities.
Q2. What volumes will be produced?
A. Near term volumes in the 10ks per month are planned with a
volume ramp greater than any other RISC processor to date. The
quick ramp is necessary since SuperSPARC is destined to be the
next flagship microprocessor.
Q3. What is the bug status of SuperSPARC?
A. SuperSPARC is clean on functional bugs. There is nothing to
impact production ramp for current customers. As with any
microprocessor there is an ongoing effort to improve performance.
Q4. Why has it taken so long to develop SuperSPARC?
A. SuperSPARC was designed to meet the needs of the mainstream
RISC computer market -- it is on target. Unlike traditional chip
programs, systems were designed and debugged in parallel so
SuperSPARC will have immediate market impact. Time-to-market
is not as important as "time-to-acceptance." Complete binary
compatibility coupled with SPARC market momentum and TI's
high volume production means SuperSPARC will have immediate
market impact. Other RISC architecture implementations coming
out today represent a strikingly different design philosophy. Many
are not true commercial processors and are therefore more difficult
to use.
Q5. What is the problem with 50MHz? When will it be available?
A. TI is announcing 33MHz and 40MHz on May 7, 1992. 45MHZ and 50MHz
will be available later in the year. Given the high demand for
SuperSPARC at frequencies lower than 45MHz, the high volume
production ramp for 33MHz and 40MHz chips and pluggable
modules became TI's first priority. Remaining tasks to achieve
45 MHz and 50MHz volume production are understood with planned
completion by TI for 4th quarter.
Q6. How many vendors will be using SuperSPARC?
A. Solbourne, ICL, Xerox and Sun have all endorsed SuperSPARC.
The chip will be made available to the general market in calendar
Q4 1992.
Q7. What can you tell us about Dynabus?
A. This is not our product. All questions on this should be directed to Xerox.
SUN/TI RELATIONSHIP
Q8. When did the relationship between Sun and TI begin?
A. The Sun/TI relationship began in 1988, when the two announced
the intent to create a partnership to design and manufacture the
next generation SPARC chip implementation.
Q9. What role did Sun and TI each play in the development of
SuperSPARC?
A. SuperSPARC is a cooperative effort between Sun and TI. Sun
and TI engineers leveraged TI's strength in submicron VLSI process
technology, packaging and manufacturing engineering and high
volume production capability with Sun's sophisticated computer
systems design and implementation expertise. Throughout this
program, integrated circuits and systems development have been
tightly coupled and coordinated in parallel to ensure the success of
this unique venture. The SuperSPARC approach has resulted in
a microprocessor that matches the needs of systems market
market better than other commercially available microprocessors.
SUPERSPARC PERFORMANCE
Q10. Why does SuperSPARC have such a low clock speed compared
to Alpha, HP-PA, etc.?
A. Because Sun/TI designed it that way. SuperSPARC is
superscalar to avoid complex systems engineering associated with
exotic clock rates greater than 100MHz. This makes SuperSPARC
workstations and servers easier to build.
Q11. Doesn't lower clock speeds equate to poorer performance?
A. MHz doesn't equal performance in the same way that RPM is
not the only factor that defines automotive performance and
responsiveness. For computers, instructions per clock, cache and
memory system, compilers, operating system and I/O system along
with MHz define the performance seen by an end user.
SuperSPARC uses superscalar multiprocessing to make computers
responsive and higher performing at mainstream clock rates. This
results in a high performance microprocessor with commercial
viability.
Q12. What is the performance of SuperSPARC?
A. TI estimates that SuperSPARC offers performance of 120
MIPS peak at 40MHz and 150 MIPS peak at 50MHz. System
SPECmarks will vary based on OEM choice of memory system, I/O
system, compiler and operating system. TI estimates:
33MHz SuperSPARC 40 SPECmarks
40MHz SuperSPARC 50+ SPECmarks
45MHz SuperSPARC w/E$ 60+ SPECmarks
50MHz SuperSPARC w/E$ 70+ SPECmarks
Note: E$= external cache which is sometimes referred to
as supercache
Q13. There have been rumors that SuperSPARC is expensive. Is this true?
A. Although TI has not announced pricing of chips, they have said it
will be targeted for high-volume production and sales. SuperSPARC is
highly integrated and reduces the chip count on a typical system from
12 to 1. Therefore, total system cost is driven down because of lower
chip count, reduction in board space and lower power consumption.
Q14. There have been rumors that SuperSPARC, with its highly complex
design and transistor count is not very efficient. Is that true?
A. Absolutely not. The fact that SuperSPARC delivers more instructions per
clock cycle -- and more MIPS per clock cycle than competing RISC chips proves
this rumor false.
Q15. Does SuperSPARC need new compilers in order to get this
anticipated performance?
A. No. SuperSPARC delivers this performance on its own and does
not need new compilers. However, we do expect new compilers to
be introduced that will further enhance SuperSPARC performance.
Q16. What's the difference between SPEC 89 and SPEC 92
SPECmarks?
A. The reason the benchmark organization SPEC chose to redefine
the SPEC benchmark was to make it more representative of application
performance. Also, many system vendors were tuning system performance
to the SPEC benchmark suite rather than to achieve balanced application
performance. SPEC 92 benchmarks were broken into two categories: SPEC Integer
and SPEC floating point. In most cases, SPEC 92 numbers turned out to be
lower than original SPEC 89 numbers. It is important to note that the SPEC
benchmark suite measures system performance, not just CPU performance.
SUPERSPARC DESIGN
Q17. Why is SuperSPARC a BiCMOS chip?
A. BiCMOS was chosen so SuperSPARC could have the density of
CMOS while selectively using BiPolar for speed critical I/O and
interconnect. In effect, we get the best of both worlds. Less than
1% of the transistors are BiPolar.
Q18. Because of a few BiPolar transistors, won't SuperSPARC be too
expensive for the mainstream?
A. There are some costs associated with marrying CMOS and
BiPolar technologies, but TI builds VLSI microprocessors like
SuperSPARC in high capacity fabrication lines proven in DRAM
production and cost-effectiveness.
Q19. Why is SuperSPARC a fully integrated single chip instead of
multiple chips?
A. A single chip with SuperSPARC's features simplifies computer
systems designs from the desktop to massively parallel systems.
Throughout its history, SPARC has brought value to the
mainstream workstation market by integrating more and more
systems features into fewer chips. The 3.1 million transistor
SuperSPARC follows that tradition. System cost is driven down
due to lower chip count, reduction in board space and lower power.
Fewer components on-board lead to greater reliability of product.
Q20. Why so many transistors for the level of performance?
A. Many of SuperSPARC's transistors were used for on-chip cache.
SuperSPARC has more than two times greater cache than most other RISC
chips. More cache means fewer trips to main memory get the instructions
and data needed by hungry user applications.
Q21. What is the expected life of SuperSPARC since it is only 32-bit?
A. It's important to separate SPARC architecture from the SuperSPARC
implementation. The scalability characteristics of the SPARC
architecture will allow it to serve the market wiell into the 21st
century. SuperSPARC is a Version 8, 32-bit SPARC architecture
implementation. According to IDC, 32-bit microprocessors like
SuperSPARC will continue to meet more than 99% of the market
need in 1995, 90% in 1997 and 80% in 2000. Thus, 64-bit will not
benefit the end user over the next several years. TI and Sun will
develop a 64-bit SPARC in accordance with SPARC architecture
enhancements developed by SPARC International. This chip will
be compatible with the existing software base.
Q22. Other microprocessors claim to have MP support, what's
different about SuperSPARC?
A. There's a dramatic difference between "support" and "complete."
SuperSPARC has complete shared memory multiprocessing on-chip --
the kind the industry wants most -- no additional engineering
or glue logic required. Most other RISC processors have "interface
hooks" to an undefined multiprocessing bus. This form of support
requires the OEM to have experienced designers to complete the
multiprocessing.
Q23. What is the difference between superpipelining used in the
R4000 and superscalar used in SuperSPARC?
A. TI and Sun believe that superscalar execution is a superior
technique to superpipelining for markets where high performance
and binary compatibility with current applications is critical.
Superscalar techniques can increase performance by executing
more instructions simultaneously while keeping clock rates
manageable. A superpipeline processor stalls frequently because it
can not group and schedule instructions. A three instruction
superpipeline processor would be quite difficult to design.
Q24. Although supescalar architectures allow the issue of multiple
instructions per clock cycle, these instructions are not staggered (as
with superpipelining). This may cause significant issue constraints
and hardware stalls. How is SuperSPARC addressing this?
A. SuperSPARC is designed to avoid these stalls by issuing
constraints via unique cascaded ALU structures, which MIPS has
not implemented.
Q25. Superpipelining requires higher clock speeds and increases
both integer and floating point performance. Superscalar improves
floating point performance but not integer performance because of
the lack of parallelism in integer applications. Does this mean
supescalar is more appropriate for technical applications and
superpipelining for better balanced, commercial applications?
A. No. Superscalar architectures do not lack parallelism in integer
applications. SuperSPARC is capable of performing three
instructions simultaneously and can be used appropriately as a
floating point microprocessor. SuperSPARC is designed to avoid
pitfalls through cascaded ALU structures. This method increases
floating point operations.
Q26. Is SMCC considering a superpipelining architecture in the
future?
A. The superpipelining architecture has limitations and SMCC has
no plans at this time to do a superpipelining implementation.
Q27. Others talk about compatibility across generations. What's so
different with SPARC?
A. The term compatibility has been made confusing by those who
don't offer full binary compatibility. SuperSPARC gives "PC-like
compatibility." All existing SPARC application binaries will run on
SuperSPARC without requiring a new compiler or recompiling
existing code. Many other processors require new code so they
aren't useful until the ISV performs work. Others use inefficient
emulators to run existing code resuling in slower application
performance. SuperSPARC runs all SPARC programs without
change except one, they run dramatically faster.
Q28. Isn't the move to multiprocessing just a coverup for lack
of uniprocessing performance improvements?
A. Multiprocessing is the new age in computer system implementation
because it makes computers more responsive and keeps clock rates
mainstream. It also provides flexibility to upgrade the performance of
a workstation or server as customer needs increase, while retaining
existing investment in surrounding disks, memory, peripherals and
compatibility of software.
SUN BUSINESS ISSUES
Q29. Will Sun base its entire workstation product line on the
SuperSPARC microprocessor alone?
A. No, but Sun is committed to future development project with
TI. In addition, Sun has SPARC projects in progress with other
vendors for future Sun product lines, not yet announced.
Q30. Why has Sun be so quiet about SuperSPARC up until
announcement time?
A. First, SuperSPARC is a a product from Texas Instruments and it
is up to them to make any announcement decisions. Second, it is
Sun policy not to discuss any unannounced products. We believe
pre-announcing products only adds to the vapor-confusion that
customers are experiencing today, and that may inappropriately set
expectations. Sun's policy is to announce when products are available
within 90 days.
Q31. When will SMCC ship SuperSPARC-based systems?
A. SMCC never comments on unannounced products.
Q32. What is the rumored Tsunami project between Sun and Fujitsu?
How does it differ from the Tsunami project between Sun and TI?
A. The rumor of a Fujitsu Tsunami CPU is just that -- a
rumor at this point.
SPARC FUTURES
Q33. What is the SuperSPARC roadmap?
A. TI and Sun have a long-term relationship to advance SPARC
state-of-the-art. SuperSPARC is the first in a series of
microprocessors that marries Sun's strengths in systems design and
implementation with TI's strengths in submicron VLSI technology,
advanced packaging and high-volume production. Ongoing
refinements to SuperSPARC include increasing performance and
reducing footprint. In 1993, the team plans to leverage TI's MCM
and fine pitch TAB packaging technologies to produce a dual
processor module that will increase performance of a single MBus
module by two times.
The continuing relationship includes a family of highly integrated
SPARC microprocessors that will accelerate SPARC's penetration
into the low-cost desktop, portable and embedded markets. Code-
named "Tsunami", this "workstation-on-a-chip" will make possible
the creation of very low-cost SPARC workstations with outstanding
performance.
COMPETITION
MIPS:
Q34. The MIPS R4000 uses a 64-bit wide instruction set. Why doesn't
SuperSPARC?
A. Based on customer input, we concluded that using a 64-bit and
128-bit data paths for performance on a 32-bit architecture was the
right approach for SuperSPARC. 64-bit architectures are useless
until the operating system can take advantage of it. A 64-bit
instruction set will not be a requirement until the mid-1990's and
SPARC will have it then. In the meantime, there is no sense in
paying for the slower 64-bit arithmetic and pointers until they are
truly needed.
Q35. The R4000 offers full MP support. It does not assume any
particular cache coherency protocol in MP system design, therefore,
many coherency protocols can be designed in a system, both in a
snoopy-based configuration and a directory-supported network-based
configuration. Is SPARC MP support better? Why?
A. MIPS has not defined a roadmap to symmetric processing and it
lacks direction with the operating system. SPARC has built-in MP
support and does not need a different chip in order to support it. It
is incorporated into the original design of SPARC version 7.0.
Through MBus, upgrades to newer technologies are easy. MIPS
doesn't offer this.
Q36. Why is SuperSPARC single-sourced when the R4000 is
multisourced?
A. SCD from SPARC International ensures that SPARC chips are binary and
plug compatible between different chip vendors and between different
chip designs. Today there are dozens of different SPARC chips
on the market, each made with a different design criteria in mind.
Multi-sourced chips from a single design tend to be limited by the least
common denominator technology. Semiconductors do not have a chance
to add their unique value, thereby decreasing the richness of innovation.
DEC/ALPHA:
Q37. What is Alpha?
A. Alpha DEC's new, proprietary RISC architecture in a single chip
implementation. It is a full 64-bit architecture in that it supports
a flat 64-bit virtual address and 64-bit registers, integers and floating
point. The Alpha chip has a 200 MHz or 5 nanosecond clock speed. It is
based on the same .75 micron CMOS and silicon technology as the VAX 6000
Model 600 which is rated at 83 MHz. Alpha will eventually consist of a
family of systems, enabling technologies and services for VMS and OSF/1
operating environments spanning the desktop to the datacenter. Alpha
will be a technology used by DEC for the next twenty-five years.
Q38. Will Alpha be part of ACE?
A. DEC positions Alpha, MIPS and Intel as the three key architectures
it intends to support throughout this decade. ACE and Alpha will overlap
with common APIs at the operating level, the same operating system (OSF/1) and
data compatibility (byte ordering). But the binary specification of
an ACE-Alpha, ACE-MIPS and ACE-Intel are different and therefore applications
will have to be recompiled between them. That means there will three DEC binary
standards supported at the desktop (Intel, MIPS ARC and Alpha) and three
workstation operating systems (OSF/1, NT and VMS). It will be very confusing
for customers and very costly for DEC.
HP PRECISION ARCHITECTURE:
Q39. HP just announced the PA-RISC 7100, a superscalar chip which
sounds like it has superior performance in comparison to your
SuperSPARC chip. Has SuperSPARC become old technology
before it is even implemented?
A. HP's superscalar chip validates Sun's position that superscalar
is the right approach for the workstation market. Since only have
working prototypes at this time, it is hard to speculate whether it
delivers balanced performance.
IBM:
Q40. IBM just announced their Model 970 Powerserver that has a
SPEC rating of 100.9 SPECmarks for a uniprocessing machine.
Doesn't that hurt SuperSPARC?
A. The IBM server is priced at $94,000 and its technology is not
applicable to high-volume desktop applications. The RS/6000 has
low integer performance making it suspect for commercial
applications. SuperSPARC delivers more balanced performance at
a lower pricetag.
Q41. How does the IBM RS/6000 superscalar ability compare to that
of SuperSPARC?
A. Like SuperSPARC, the IBM RS/6000 has the superscalar
advantage of being able to process more than one instruction in
parallel. The processor can execute a maximum of four instructions
per machine cycle. It can execute one branch instruction, one
condition register logic instruction, and one each of a floating-point
and a fixed-point instruction. As a result, it rarely achieves four
instructions per clock. SuperSPARC has abundant resources and
frequently achieves three instructions per cycle. We estimate a
typical IPC of 1.4 to two, depending on system design and
compiler.
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