applied numeric expert looking for a new project

[Tom Lynch]

Thomas Walker Lynch 
U.S. phone: 512-775-9245 
email: lynchaths.com 


Skills 
Hardware: Architecture, Microcode, Logic Design, Circuit Design, Verification,
Math Algorithms 
Software: Architecture, Algorithm Design, Compilers, C++, Mathematica, Assembly,
Math Library 
Project: Methodology, Small Team Management, Education, Training, Documentation


Education 
M.S.E.E., 1996, University of Texas at Austin. Advisor Earl Swartzlander Jr.
Thesis, Binary Addition. (Presented first deterministic solution for Carry Skip
adder optimization) 
B.S.E.E., 1986, University of Texas at Austin and the University of Iowa 

THS Inc. 1996-date 
Developed x86 numeric processor emulator.  Developed microcode for advanced
numeric functions.  Developed technology for formal verification of software
and microcode.  Developed compiler technology for verified result calculations.
  Developed network security technology. 

AMD, 1986-1996 
Member of Technical Staff, Advanced Architecture Department.   Contributed to
 7 processors: K7, K6, K5, Am80846, Am79410, Am29050, and the Am29000.  Block
lead on K7 superscalar, numeric microcode lead on K5 superscalar.  Clock designer
and smart card interface on Am79410.  Data path and control for 12 functions
on Am29050.   

Pre-Graduate, 1978-1986 
Wrote C++ spice simulator. Designed and built IBM PC peripheral security board
with x86 assembly code firmware. Developed a design for cycle based simulator
in PLS. Built electrode connectivity tester. Built rack mount medical instrumentation
amplifiers. Performed PDP11/PDP8 servicing. Wrote Techtronix 4014 GUI. Performed
audio and stage equipment repair.

Patents

1. (Pending) Lynch; Thomas W. Encapsulated Code Structure Intermediate Compiler
Language, Programming Process, and Tools

2. (Pending) Lynch; Thomas W. System and Method for Supporting Multimedia Communications
Upon a Dynamically Configured Member Network

3. (Pending)l Lynch; Thomas W. Virtual Setting Video Generation System and
Method of Operation Therefor

4. (Pending), Lynch; Thomas W. Symbiotic Computing System and Method of
Operation Therefor

5. US6009511 Lynch; Thomas W. Apparatus and Method for Tagging
Floating Point Operands and Results for Rapid Detection of Special Floating

Point Numbers

6. US5930820 Lynch; Thomas W. Data cache and method using a stack memory
for storing stack data separate from cache line storage

7. US5930492 Lynch; Thomas W. Rapid pipeline control using a control word
and a steering word

8. US5887185 Lynch; Thomas W. Interface for coupling a floating point unit
to a reorder buffer

9. US5859998 Lynch; Thomas W. Hierarchical microcode implementation of
floating point instructions for a microprocessor

10. US5829031 Lynch; Thomas W. Microprocessor configured to detect a group
of instructions and to perform a specific function upon detection

11. US5829028 Lynch; Thomas W.; Yard; Christopher J. Data cache configured
to store data in a use-once manner

12. US5828873 Lynch; Thomas W. Assembly queue for a floating point unit

13. US5819067 Lynch; Thomas W. Computer system configured to translate a
computer program into a second computer program prior to executing the computer
program

14. US5771362 Bartkowiak; John G. , Lynch; Thomas W. Processor having a
bus interconnect which is dynamically reconfigurable in response to an instruction
field

15. US5721945 Mills; Andrew , Ireton; Mark A. , Lynch; Thomas W.
Microprocessor configured to detect a DSP call instruction and to direct a DSP
to execute a routine
corresponding to the DSP call instruction

16. US5285406 Lynch; Thomas W. , McIntyre; Steven D. High speed mixed radix

adder

17. US5267186 Gupta; Smeeta , Perlman; Robert M. , Lynch; Thomas W.,
McMinn; Brian D. Normalizing pipelined floating point processing unit

18. US5206828 Shah; Salim A. , Lynch; Thomas W. Special carry save adder
for high speed iterative division

19. US5095458 Lynch; Thomas W. , McIntyre; Steven D. Radix 4 carry
lookahead tree and redundant cell therefor.


20. US5128891 Lynch; Thomas W. , McIntyre; Stephen D. ,Tseng; Ken, Shah;
Salim A. , Hurson; Tony High speed divider with square root capability

21. US5058048 Gupta; Smeeta, Perlman; Robert M. , Lynch; Thomas W. ,McMinn;

Brian D. Normalizing pipelined floating point processing unit

22. US5053631; Perlman; Robert M. ,Sobel; Prem , McMinn; Brian D.,Thaden;
Robert C. , Tamura; Glenn A. , Lynch; Thomas W. , Vesgesna; Raju. Pipelined

floating point processing unit.

Publications

J Strother Moore, Thomas W. Lynch, Matt Kauffman, "A Mechanically Checked
Proof of the AMD5k86 Floating-Point Division Program", IEEE Transactions on

Computers, September 1998.

Thomas W. Lynch and Mike Schulte, "Software for High Radix Online Arithmetic"
- 
Journal of Reliable Computing.

Thomas W. Lynch, "High Radix Online Arithmetic for Credible and Accurate 
General Purpose Computing", Real Numbers and Computers, April 4-6,
1996, Saint-Etienne, France.

Thomas W. Lynch, et. al, "The K5 Transcendental Functions", Proceedings of the

12th Symposium on Computer Arithmetic, July 19-21, 1995, Bath, England, 
IEEE Computer Society Press, 1995.

Thomas W. Lynch, "The Spanning Tree Adder", IEEE Transactions on Computers,

IEEE Computer Society Press, August 1992.

Thomas W. Lynch, "Redundant Cell Adder", Proceedings of the 10th Symposium on

Computer Arithmetic, IEEE Computer Society Press, Grenoble, France, 1991.

Thomas W. Lynch "Binary Adders". UT masters thesis.

Thomas W. Lynch, "The Energy Content of Knowledge", Post-Proceedings of the

Physics of Computation Workshop, Dallas Texas, IEEE
Computer Society Press, 1992.

Thomas W. Lynch, "A Formalization of Computer Arithmetic", Proceedings of the

Third International IMACS-GAMM Symposium on Computer Arithmetic and Scientific

Computation (SCAN-91). Oldenburg, Germany, Oct. 1-4 1991, Elsevier 1992.



References Furnished Upon Request