Time ordering of IEEE-754 exceptions

[David G Hough at validgh]

A related issue which recently arose has to do with SIMD instructions:
if two floating-point instructions execute at exactly the same time,
what happens if one traps and the other does not.    From the programming
environment point of view, if the language construct which launched both
instructions manifested their parallelism, then presumably there wouldn't
be any way to separate their exceptional consequences.    But if the 
programming language specified two sequential operations that were then
combined by an optimizer into one SIMD instruction, then a trap handler
might not be able to tell which sequential operation trapped.    Making that
work would require some cooperation between the hardware, system software,
and debugger designers.