costs of floating-point implementation

[uunet!sam.math.ethz.ch!moesli]

I'm looking for some information on implementations of
floating-point arithmetic in microprocessors.
Are some reports or informal papers available on this topic?
I'm actually looking for  f a c t s  on the old and cumbersome discussion by
numerical analysts on denormalized numbers. Especially interesting are 
the costs with respect to chip design, chip area and cycle delay.
No company secrets are required, just some approximate numbers (in percent of
the fpu costs).
How much (in %) would denormalized numbers blow up a software implementation
(source size and running time)?

Regards

Bernd Moesli
moesliasam.math.ethz.ch
Seminar for Applied Mathematics
Swiss Federal Institute of Technology Zurich
ETH-Zentrum
Fliederstr. 23
CH - 8092 Zuerich