Quads on Power2

[Fred Tydeman]

1) Power2 documentation says that quad floating-point must be quad
aligned (last 4 bits of address be 0000).  Otherwise, an alignment
check trap is taken (but I believe that an implementation may go ahead
and allow misaligned quads without taking the trap).
 
The load/store is into a pair of double precision registers (there is
no requirement that they be an even/odd pair) and they can be f31+f0.
 
2) I believe that the compilers force quad alignment for quads by
default.
 
These are not IBM's views, these are the personal ones of:
Fred Tydeman, computer consultant at (512) 255-8696 after April 15th
Internet: tydemanaibmpa.awdpa.ibm.com    uucp: uunet!ibmsupt!tydeman