quad aligned load/stores

[Dennis Brzezinski]

  The V9 SPARC  and IBM POWER2 define  quad loads and stores.  
V9 SPARC loads to a 128 bit register.  IBM POWER2 loads two double precision
FP numbers to an even-odd register pair.


1) Do you know what quadword convention  IBM's POWER2(which has quad ld/st) 
follows?  i.e. does IBM allow doubleword alignment?  does it handle memory 
block crossings in hardware?(extra tag check?) Will SUN handle non-quad
aligments with hardare or software??

2) Do SUN/IBM use any compiler directives to insure quad alignment?

3) Do you have any data on how useful quad load/store is when only quadword 
aligment is supported?  i.e. what percentage of codes can use this.

4) Do you "believe" in this stride=1 solution, or are there compelling reasons
for a more general high bandwidth memory system that does not mandate stride=1?


Dennis Brzezinski
HP Laboratories
A Private posting.