announcements about SPARC and Pentium
David G. Hough on validgh
dgh
Mon Mar 22 22:23:04 PST 1993
For those who want to know exactly what was said,
here are less details than one might like, and more details than one might like.
(I'm beginning to think that SPEC should require separate results
for "-O only" as well the current results that permit optimization options
to be optionally optimized for each specific benchmark and compiler).
What's not said is how to
get similar numerical results, without compromising performance,
on RISC and x86 floating-point implementations,
whenever Solaris, NT, Taligent, NextStep, etc., become available on both.
=======================================================================
SMCC UNVEILS SPARC(R) CPU ROADMAP
MOUNTAIN VIEW, Calif. -- March 22, 1993 -- Sun Microsystems Computer
Corporation (SMCC) today unveiled the industry's most comprehensive CPU
design strategy based on the SPARC(R) microprocessor architecture.
Called the SPARC CPU Roadmap, it provides details on nine CPU designs
currently under development that are grouped into three microprocessor
design families. Two of the families -- microSPARC(TM) and
SuperSPARC(TM) -- have already resulted in CPU implementations shipping
in volume from one of SMCC's microprocessor foundry partners, Texas
Instruments. The third family, called UltraSPARC(TM), heralds SMCC's
expansion into 64-bit SPARC implementations.
Microprocessor products resulting from this strategy power current and
future SMCC computer systems, providing scalability and binary
compatibility across all product lines running the industry leading
Solaris 2 distributed operating environment. As part of its SPARC
Technology Business, SMCC is making resulting CPU designs and
microprocessors available to the open market.
"Unlike companies making only chips, SMCC -- as a system supplier --
really understands the most critical issues of those buying
microprocessor-powered computers. Thus, all nine of these designs
leverage our strengths in CPU logic design, computer system design,
compiler development, operating system expertise and our knowledge of
application software needs," said Derek Meyer, director of SPARC
Marketing for SMCC.
The microSPARC Design Family
The microSPARC design family -- a "workstation on a chip" -- will meet
CPU requirements for the low-cost desktop and server, portable and
embedded markets. These requirements include high system-level
integration on-chip, volume-oriented packaging, strong integer
performance, low power consumption, and low cost.
The microSPARC design family is composed of three design "points,"
called microSPARC, microSPARC II and microSPARC III. Each point will
result in multiple CPU implementations. The microSPARC family is
expected to deliver performance scaling to 150 Dhrystone MIPS and 100
SPECint 92.
A new floating point unit, an enhanced integer unit, and power
management features are design enhancements to microSPARC II, targeted
for 1994. The microSPARC III designs, slated for 1995, will use faster
transistors and add external cache memory.
The single-scalar, single-pipeline microSPARC designs are 32-bit
architectures based on Version 8 of the SPARC Architecture published by
SPARC International, thus preserving end user investment in SPARC
application software. MicroSPARC processors, manufactured by Texas
Instruments, power Sun's recently announced SPARCclassic(TM) and
SPARCstation LX(TM) workstations.
The SuperSPARC Design Family
Like microSPARC, the SuperSPARC family also includes three design
points, called SuperSPARC, SuperSPARC+ and SuperSPARC II. They are
32-bit Version 8 designs optimized for high-volume multiprocessing,
high performance per clock cycle (SPECint/MHz) and an integer/floating
point balance for outstanding application performance. Resulting CPU
implementations will include versions beyond 100 SPECint 92 and
approaching 200 SPECfp 92.
SuperSPARC+ designs, available later this year, will incorporate faster
transistors. SuperSPARC II designs, slated for 1994, will incorporate
enhanced integer and new floating point units, plus a dual-launch
floating point, increasing overall floating point performance.
SuperSPARC's integrated multiprocessing features, and MBus or XDBus(TM)
upgradeability, currently support a wide range of desktop and server
products. SuperSPARC microprocessors, manufactured by Texas
Instruments, serve as the CPU architecture for SMCC's SPARCstation(TM)
10 workstation and server product lines, as well as the company's
recently introduced SPARCcenter(TM) 2000 server, which offers up to
20-way multiprocessing. These systems also run the Solaris 2 operating
environment.
The UltraSPARC Design Family
The UltraSPARC design family is SMCC's next-generation 64-bit SPARC
technology, based on the Version 9 architecture specification from
SPARC International. The Version 9 architecture supports upward
compatibility with all current 32-bit SPARC applications. Resulting
CPU implementations will power future Sun(TM) workstations and
servers. UltraSPARC microprocessors are four-scalar, four-level metal
designs, featuring dual-launch floating point units and providing both
uni- and multiprocessor support.
The family features three design points, UltraSPARC I, UltraSPARC II
and UltraSPARC III. Each will include multiple CPU implementations.
UltraSPARC I and II will utilize .5 micron CMOS processes, while
UltraSPARC III uses advanced .5 to .4 micron BiCMOS process
technology. This family will ultimately scale in performance, ranging
from 700 to 1000 SPECint 92/SPECfp 92 and beyond. CPU implementations
based on these designs are expected to arrive between 1995 and 1997.
"The SPARC Architecture is an industry standard technology," said
Meyer. "This roadmap outlines unsurpassed scalability and will enable
SPARC adopters to deliver the widest range of compatible client-server
solutions".
SPARC, The Leading RISC Architecture
According to market research organization International Data
Corporation (IDC), SPARC systems represent 56 percent of 1992 RISC
workstation/workstation server shipments. Products based on SPARC
technology are available from more than 34 system vendors and seven
microprocessor/ chipset vendors.
=======================================================================
> Date: Mon, 22 Mar 93 14:17:43 PST
> From: jwreillyamipos2.intel.com (Jeffrey Reilly)
> Subject: Intel Pentium(tm) Processor SPEC Dislcosure
>
> Intel held a press announcement today (3/22/92), that included performance
> information on the Pentium(tm) Processor. The SPEC information presented
> included:
>
> Processor: 66MHz Intel Pentium Processor
> SPECint92: 64.5
> SPECfp92: 56.9
> SDET Peak: 476.8
>
> Processor: 60 MHz Intel Pentium Processor
> SPECint92: 58.3
> SPECfp92: 52.2
>
> * Results based on an early Intel Pentium-CPU based system. Higher performance
> is expected from production-level Intel Pentium processor-based systems (e.g -
> non-beta compilers).
>
> A Performance Brief should be obtainable from Intel Literature
> (1-800-548-4725), "Pentium Processor Performance Brief" (order number
> 241557-001).
>
> Below are the configurations for the 66Mhz Pentium Processor. The configuration
> for the 60MHz Pentium Processor was the same (except for the CPU).
>
> Enjoy!
>
> Jeff
>
> Jeff Reilly Performance Benchmarking And Analysis
> jwreillyamipos2.intel.com Intel Corporation
> (408) 765 - 5909 Santa Clara, California
> ============================================================================
>
> Results Page: CINT92
> Company name Intel Corporation
> Machine name Pentium Processor/66
> Model No. Pentium Processor/66
> CPU 66MHz Intel Pentium Processor
> FPU Integrated
> # of CPUs 1
> Cache "8KB(I)+8KB(D) on chip, 256KB(I+D) off chip"
> Memory 64MB
> Disk 2 1.2GB DEC DSP SCSI
> Other hardware 2 DPT HD Controller, 4.5MB Cache
> OS Version UNIX SVR4.2
> C Compiler Intel Reference C Compiler (BETA RELEASE 1/27/93)
> Other software None
> File system AFS
> Tuning parms See Notes
> BG load None
> System state Multi-user, single user log-on
> Hardware avail Within 6 months
> Software avail Within 6 months
> Date tested Feb-93
> Tested by Intel
> at location Santa Clara, CA
> SPEC license 14
> SPECint92 64.5
> Benchmark Time SPECratio
> ---------------------------------
> 008.espresso 37.6 60.4
> 022.li 70.6 88.0
> 023.eqntott 20.2 54.5
> 026.compress 66.9 41.4
> 072.sc 47.2 96.0
> 085.gcc 87.0 62.8
>
> Notes/Flags
> -----------
> Note0 "008.espresso: -O -tp p5 -w -mem -ip -W0,-mP20PT_disamb_types=TRUE"
> Note1 "022.li: -O -tp p5 -w -ip -W0,-mP20PT_disamb_types=TRUE -W0,-mP20PT_conditional_lim=TRUE"
> Note2 "023.eqntott: -O -tp p5 -w -ip -W0 -DSYSV -ip -W0,-mP2OPT_conditional_lim=TRUE"
> Note3 "026.compress: -O -tp p5 -w -mem -ip -W0,-mo_block_loops,-mo_block_size=25 -W0,-mP2OPT_conditional_lim=TRUE"
> Note4 "072.sc: -O -tp p5 -w -DSYSV3 -DSIGVOID -DSIMPLE -Xa -ip -mem -W0,-mP2OPT_disamb_types=TRUE"
> Note5 "085.gcc: -O -w -W0,-ip_no_inlining -W0, -ip_nocloning -ip -pad -W0,-mP2OPT_disamb_types=TRUE"
> ========================================================================
> Results Page: CFP92
> Company name Intel Corporation
> Machine name Pentium Processor/66
> Model No. Pentium Processor/66
> CPU 66MHz Intel Pentium Processor
> FPU Integrated
> # of CPUs 1
> Cache "8KB(I)+8KB(D) on chip, 256KB(I+D) off chip"
> Memory 64MB
> Disk 2 1.2GB DEC DSP SCSI
> Other hardware "2 DPT HD Controller, 4.5MB Cache"
> OS Version UNIX SVR4.2
> C Compiler Intel Reference FORTRAN 77 And C
> f77 Compiler Compiler (BETA RELEASE 1/27/93)
> Other software None
> File system AFS
> Tuning parms See Notes
> BG load None
> System state "Multi-user, single user log-on"
> Hardware avail Within 6 months
> Software avail Within 6 months
> Date tested Feb-93
> Tested by Intel
> at location "Santa Clara, CA"
> SPEC license 14
> SPECfp92 56.9
> Benchmark Time SPECratio
> ---------------------------------
> 013. spice2g6 489.4 49.0
> 015. doduc 37.8 49.2
> 034. mdljdp2 113.5 62.5
> 039. wave5 95.5 38.7
> 047. tomcatv 38.8 68.3
> 048.ora 115.3 64.4
> 052.alvinn 68.7 111.9
> 056.ear 196.6 129.7
> 077. mdljsp2 111.3 30.1
> 078. swm256 310.8 40.9
> 089. su2cor 267.8 48.2
> 090. hydro2d 246.4 55.6
> 093. nasa7 348.4 48.2
> 094. fpppp 146.2 62.9
>
> Notes/Flags
> Note0 013.spice2g6: -O -tp p5 -w -DSYSV
> Note1 015.doduc: -O -tp p5 -w
> Note2 "034.mdljdp2,047.tomcatv,078.swm256,093.nasa7: -O -tp p5 -w -ip -mem -pad"
> Note3 "039.wave5: -O -tp p5 -w -save -ip -mem -pad -W0,-mP2OPT_disamb_types=TRUE"
> Note4 "048.ora: -O -tp p5, -ip -mem -W0,-mo_block_loops,-mo_block_size=8"
> Note5 "052.alvinn: -O -tp p5, -ip -mem -W0,-mo_block_loops,-mo_block_size=16"
> Note6 "056.ear: -O -tp p5 -w -ip -mem -pad -W0,-mP2OPT_disamb_types=TRUE -W0,-mP2OPT_conditional_lim=TRUE -W0,-mo_siblings_limit=25,"
> Note7 " -ip_inline_max_states=1200,-ip_inline_max_bblocks=50"
> Note8 "077.mdljsp2: -O -tp p5, -ip -mem -W0,-mo_block_loops,-mo_block_size=30"
> Note9 "089.su2cor: -O -tp p5 -w -ip -mem -W0,-mP2OPT_disamb_types=TRUE -W0,-mP2OPT_conditional_lim=TRUE"
> Note10 "090.hydro2d: -O -tp p5 -w -save -ip -mem -W0,-mP2OPT_conditional_lim=TRUE"
> Note11 "094.fpppp: -O -tp p5 -w -mem -W0,-mP2OPT_disamb_types=TRUE -W0,-mo_block_loops,-mo_block_size=25"
>
> Flag summary:
>
> For CINT92 and CFP92:
>
> -O well-known machine independent optimizations (for example, loop unrolling
> constant folding, etc)
> -tp p5 optimize for the Intel Pentium(tm) processor
> -w suppress warning messages
> -mem optimizations to improve caches hits and # of memory references
> -ip optimize to eliminate call overhead and create opportunities for
> further optimizations
> -mP20PT_disamb_types=true
> allows the compiler to better disambiguate pointer dereferences
> (e.g. - assumes a pointer type is never cast to a different pointer
> type)
> -mP20PT_conditional_lim=true
> Do perform loop invarient code motion on conditionally executed
> loops
> -mo_block_loops/size
> Specifies the block size to use in blocking loops.
> -Xa Specify ANSI Standard C with extensions
> -ip_no_inlining
> Inhibit -ip inlining
> -ip_nocloning
> Inhibit -ip cloning
> -pad analyze and reorder memory layout for variables and arrays
>
> For CFP92 only:
> -save variable impicitly attributed as SAVE values
> -ip_inline_maxstates/blocks
> Specifies the maximum size in instructions/branches allowed for a
> function to be inlined
> -mo_siblings_limit
> Specifies maximum number of nested loop -mem examines
> ------------------------------------------------------------------------
> SDET configuration:
>
> The same as the CINT92 configurations with the exception of:
> 5 SCSI DISK controllers, DPT PM2012B/90 (4.5MB writeback cache, 32 block
> lookahead)
> 10 SCSI disks, DEC DSP 3105 disks
>
> 2 disks per controller, OS/swap on first disk, first controller.
>
> 1 248.3
> 2 416.2
> 3 430.3
> 4 476.8
> 5 453.4
> 6 452.8
> 8 444.4
> 12 434.7
> 16 428.3
> 20 426.0
>
> NPROC=1800, MAXUP=1600, BUFHWM=2048, NHBUF=256
> All inode parameters set to 1300.
> ---------------------------------------------------------------------
> Ratios for Pentium Processor/60:
> CINT92
> 008.espresso 54.7
> 022.li 78.7
> 023.eqntott 49.5
> 026.compress 37.6
> 072.sc 86.5
> 085.gcc 56.8
> SPECint92 58.3
>
> CFP92
> 013.spice2g6 44.6
> 015.doduc 45.5
> 034.mdljdp2 56.9
> 039.wave5 34.9
> 047.tomcatv 62.1
> 048.ora 58.0
> 052.alvinn 95.5
> 056.ear 116.8
> 077.mdljsp2 27.2
> 078.swm256 36.9
> 089.su2cor 45.1
> 090.hydro2d 49.7
> 093.nasa7 43.5
> 094.fpppp 70.4
> SPECfp92 52.2
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