An IEEE Question

[David G. Hough on validgh]

> Note:  The Intel  80x87 family uses a single set of  status flags and it
> is "level-sensitive".  The Motorola 6888x family uses two sets of status
> flags and it is "edge-triggered".

Does x87 really work this way?
In any case, 
from the beginning of 754 it was always expected that the required software 
interface could be satisfied by various hardware implementations.   The 
single-flags implementation
is minimal; it requires system software intervention in order to provide
the user interface that the 68k and SPARC provide directly via TEM and AEXC,
the trap enable mask and the accrued exception bits.

Designs like x87 depend on hardware flags with two states:

	A) no exception encountered, trap on first one
	B) one or more exceptions encountered, do not trap on subsequent ones

The hardware flags are initialized in A state, 
and when an exception occurs,

if its software TEM is off:
	its software AEXC is set on
	the hardware flag is reset to state B to ignore subsequent exceptions
if its software TEM is on:
	its software AEXC is not changed
	a user level trap occurs
	the hardware flag is reset to state A to catch subsequent exceptions

So every exception causes a trap if TEM is on, but only the first
if TEM is off.

The Sun-3 FPA hardware worked this way for the inexact exception.
I wrote the system software to conceal it.   Some of the evidence may still
be around on Sun-3's in the /usr/lib/ffpa.il or /usr/lib/ffpa/libm.il files.
Other IEEE exceptions trapped
all the time, which worked since they were rare events - except 
sometimes underflow.