results from HP

[Don Steiss]

>From: uunet!Eng.Sun.COM!dghauunet.UU.NET (David Hough)
> .
> .
> .
>  The FP coprocessor is built with TI's 0.8 micron EPIC-2 CMOS process and
>  designed by TI's ASIC group. It has 640K transistors and uses a 207 pin PGA. 

The FP coprocessor was designed by the ASP group at TI, which is separate from 
our ASIC group.  ASP builds custom datapath and cache products.

>  the architecture to add 5-operand FP mul-add and mul-sub compound 
>  instructions like IBM, integer multiply, and doubled FP registers from 16 to 

The 5-operand instructions are two independent IEEE operations and each
of the two results is rounded separately.

Don Steiss, Texas Instruments, Dallas TX
steissatidmmpl.csc.ti.com