Very impressive results from HP

[David Hough]

In case you haven't heard, rumor is that HP will be announcing a
66 MHz $20000 PA-RISC desktop next week that attains a SPECmark of 55 or 72,
depending on which rumor you believe.  For half that amount you can get
a desktop that only achieves 43 or 55.  Somebody at Sun found the following
on USENET:

  The CPU chip is a simple 5-stage RISC pipeline much like the R3000. It has 
  577K transistors and is fabbed with HP's CMOS26 1 micron process. It is 
  packaged in a 408 pin PGA package. It has a 64-bit data path to the external 
  D-cache, and a separate 32-bit path to the I-cache (address lines are 
  separate for the caches), 32-bit multiplexed data/address lines to memory. 
  Cache control logic is on chip. Cache size of 4K to 2MB for D and 1 MB for I 
  are supported. 
  
  They use 12 ns SRAMs with transparent latches in their 66 MHz design, with 
  controlled impedance, matched length PCB traces. The CPU uses a 2X system 
  clock and generates cache addresses early in the cycle. They can map large 
  sections of virtual memory contigously for things like frame buffers.
  
  The FP coprocessor is built with TI's 0.8 micron EPIC-2 CMOS process and
  designed by TI's ASIC group. It has 640K transistors and uses a 207 pin PGA. 
  Add and multiply have a 3-cycle latency, and a new op can be issued every 2 
  cycles. Divide takes 12 cycles. 
  
  They presented measured data for 50 and 66 MHz systems using 128KB I and 
  256KB D caches. 
  
  			50 MHZ		66 MHz
  
  Overall SPECmark	42.8		55.3
  SPECint		38.1		49.9
  SPECfp		46.2		60.1
  
  They now call the architecture PA-RISC as opposed to HPPA, since it has been
  licensed and "is no longer HP's proprietary architecture". They have extended
  the architecture to add 5-operand FP mul-add and mul-sub compound 
  instructions like IBM, integer multiply, and doubled FP registers from 16 to 
  32.