SPARC quad format

[Earl Killian]

   Date: Tue, 4 Jun 91 11:20:33 PDT
   From: dghavalidgh.com (David G. Hough on validgh)

   6) At least one hardware designer thought that although it would take a
   little longer to get a quad precision adder implemented, it would not
   take so much longer that it was worthwhile doing a klugey type of quad
   precision such as composing one from two doubles.  Such arithmetic
   can't be both fast and clean, especially if exceptions are to be
   handled in a reasonable way.

I agree that if you decide to build a 112-113 bit datapath, it's not
much more difficult to design than building a 53-bit datapath.  But
that misses the point; it does take more than twice the space, which
is likely to relegate quad precision to software for a very very long
time.  If people really wanted quad, and want tolerable speed, then
they probably would want precision 106-bit, because that could be done
in hardware using two passes through an existing 53-bit datapath.

So it seems to me that you can have the extra bits and be forever so
slow that no one will ever use it, or you can cut back slightly and
have a chance that someday it will be fast.

Of course you might argue that 80-bit hardware has the datapath
required to do 112-113 bit quad with two passes.  True, but it's not
clear 80-bit has much future either.