IEEE quad precision

[Jerry Huck]

> I was recently asked about an attempt to standardize a 128 bit floating
> point format through an IEEE committee 1754.  Rumour has it that this
> format has already been implemented in the HP Precision Architecture.
> Does anyone know what the charter of this committee is, and whether or
> not a definition of the 128 bit floating-point format is available?

wrt PA-RISC (HP's most current name for HP Precision Architecture), it
defines a 128-bit "quad" precision format that complies with IEEE/ANSI
754's requirements for a double extended format.  It is the obvious
definition with 1 sign bit, 15 exponent bits, and 112 (128-15-1)
fraction bits.  It also uses a hidden bit.  None of the current
PA-RISC processors implement quad operations.  Languages currently
access quad functionality through procedural interfaces.

A look at the latest draft proposal for P1754 shows an
identical "quad" format.

IEEE standard group 1754 is defining a standard open microprocessor
architecture based on the SPARC architecture.  Inquires to
philasparc.com (chairman of the working group).

> Thanks in advance for any information.
> 
> -- 
> Tom MacDonald
> tamacray.com
> uunet!cray!tam
> 

Jerry Huck
Information Architecture Group
Hewlett-Packard