much more on 8087 patent, including extracts from patent itself
David Hough
validgh!sun!Eng!dghaSun.COM
Thu Jan 24 14:28:42 PST 1991
I got lots of mail about this, none of it directed back to numeric-interest,
so here it is with identification removed. First some Sun stuff, then
the 8087 stuff, including actual patent extracts for the 8087 and later
products, ALL IN CAPS TO MAKE IT
HARD TO READ. Note that the patent
inventors include Lai, Saini, and Valerio, who are on numeric-interest.
[I hope patent applications aren't copyrighted, and that nobody has a patent
on using copyright to protect products.]
------------------------------------------------------------------------------
SUN STUFF:
------------------------------------------------------------------------
Why couldn't the Sun compiler have checked to see if a FPU was available
and disabled that option (make it ineffective) if it wasn't? Was there
some architecture problem with this?
------------------------------------------------------------------------------
[dgh: It was decided for Sun-3 that the default compilation option must
run with adequate performance on all Sun-3's, because of network considerations:
executables might be compiled here and run there. Since 3/50 wasn't going to
have a standard 68881, the default compilation option was -fsoft.
For recent unbundled compiler products,
we added an option "-native" to compile for
the fastest hardware on the compile-time system, and included it in the macro
option "-fast" which is intended to replace "-O" in the minds of people who refuse
to read more than one paragraph of documentation. "-native" is still not the
default, and for the same reason: code compiled on a sparcstation that exploited
the hardware sqrt instruction would run real slow on a 4/1x0 or 2x0 with
Weitek 1164/5 floating point.]
------------------------------------------------------------------------------
What's the market for a SPARC that has a built-in really slow float
box, with the pins to connect it to a conventional SPARC float chip if
you want speed? (A config register would select which opcodes went to
which floatbox: fxxx or cpxxx.) I bet a lot of cheap machines would
like this. How hard would it be to do, if your design goal was
"faster than software can emulate it, only add 20% or less to the cost
of the CPU chip"? Suppose you implemented that multiply-and-add model
in microcode (a state sequencer) using a small, e.g. 16x16 or 8x8
multiplier and the usual 32-bit integer adder? Since there are
typically several adders in a SPARC CPU, you might be able to use
several of them at once if useful e.g. for doubles.
------------------------------------------------------------------------------
[dgh: I heard that 85% of 4/1x0's had hardware floating point,
so the low base sticker
price was mostly psychological. As for really low-cost SPARC systems, I would
guess that even providing board space for an optional chip and extra power supply
for it would eventually cost as much as the chip. "Low-cost" and "configurable" are
antithetic - I imagine if DRAM were cheaper, 4/20 SLC systems would only come
in one 16 MB configuration instead of 8, 12, or 16. My guess is that there
isn't a lot of extra room in the power, heat, and real estate budget of the SLC -
it's really crammed onto the back of the monitor. validgh.com, by the way,
is a 16 MB SLC running SunOS 4.1.1.
A more reasonable approach to low
cost will eventually be to have everything except the DRAM on one chip.
You could in
principle have a power- and heat- and pin-compatible plug-in upgrade CPU,
but Sun has shown relatively little interest in that kind of chip upgrade
solution, e.g. upgrading a Sun-2 to 68020 or a Sun-3 to 68030 was never
pursued because the performance enhancement was always disappointing relative
to the cost - you needed to upgrade the rest of the system as well, or at least
the CPU board.]
------------------------------------------------------------------------------
INTEL STUFF:
-------------------------------------------------------------------------------
> Stack addressing: the 8087 allows its eight extended-precision data registers
> to be addressed either by number 0-7 in conventional general register fashion
> or as stack operands.
I'm not sure what you mean by this, but if you mean that the registers
can be accessed without being indirected by the value of the top of stack
register then this is not right. All registers are stack registers
although it is possible to access registers other than the top two elements
of the stack. Maybe this is what you meant. However, the statement that
the registers can be "addressed... in conventional general register fashion"
is misleading. All registers can only be accessed relative to the top of
stack value (TOP).
-------------------------------------------------------------------------------
> Stack addressing: the 8087 allows its eight extended-precision data registers
> to be addressed either by number 0-7 in conventional general register fashion
> or as stack operands.
Not true. Would that it were! Compilers would be a lot happier
if it just had 8 registers.
The registers are *always* addressed as a stack. You can pull out
any value from the "top" (reg 0), "next to top" (reg 1), etc down to
reg 7. You could only write to the top, though; you got a choice
(most of the time) whether to write to it or to push onto it (turning
reg 0 into reg 1, putting your new value into the new reg 0).
You couldn't add two numbers and put the result anywhere but reg 0,
so register variables were just out of the question.
The 387 added
more instructions, that would let you use things other than TOS as
destinations. I don't think it's fully symmetrical though, and
possibly never will be.
------------------------------------------------------------------------
All the GE 600 series machines, from the 605 (which I think dated from 1958)
615, 625, 635, and 645 (the original Multics machine)
through until the computer division was sold to Honeywell about 1970,
and then all the Honeywell machines that continued the line, including
6050, 6060, 6070, 6080, 66/60, 66/80,68/60, 68/80, and more recent
machines produced in the 1980's which I did not have any contact with,
i.e. all the large scale systems produced by both GE and Honeywell,
were 36 bit machines that used a floating point accumulator that had
a mantissa which was a double word (72 bits) wide, and an exponent (8 bits)
that was stored in a separate register. Floating point numbers in memory
were a single word wide, single precision, with a 28 bit mantissa and 8 bit
exponent, or a double word wide, double precision, with a 56 bit mantissa
and an 8 bit exponent. Both the exponent and mantissa were represented in
2's complement. Operations were between memory and the accumulator,
and used the full extended length of the accumulator both with single
precision and double precision memory operands.
In the late 1970's there was a machine in this series, internally called the
Med 6 (I forget the commercial name) which had 8 floating point registers
of the extended format, rather than the single accumulator. I no longer have
a manual, and don't remember the details, but I think that if you used the
floating point instructions used by the rest of the line, then floating point
register 0 was implied, and new floating point instructions were provided
for floating point operations that specified which floating point register
was to be used for register-memory operations, and also provided register-
register operations. I do not remember any ability to use the floating point
registers as a stack.
------------------------------------------------------------------------
4/5/1 (Item 1 from file: 25)
2071435 3047304
E/ APPARATUS AND METHOD FOR CONVERTING FLOATING POINT DATA FORMATS IN A
MICROPROCESSOR
Inventors: Saini Avtar (US)
Assignee: Intel Corp Assignee Codes: 42458 Document Type: UTILITY
Applic Applic Patent Issue
Number Date Number Date
--------- ------ ---------- ------
Patent: US 288433 881222 US 4949291 900814
Priority Applic: US 288433 881222
Abstract:
An apparatus and method for converting the format of the exponent portion
of a biased floating point number in a microprocessor is disclosed. The
present invention allows a conversion to be performed as the data is being
loaded. Decoding circuitry first determines when floating point data is
about to be loaded. A constant, which corresponds to the type of conversion
to be performed, is then generated from a ROM. The data and constant are
added and the result, representing the converted exponent is stored in an
exponent resister within one clock period.
Claim:
D R A W I N G
1. In a computer system which includes a two-phase clocking means, a
data format conversion apparatus for converting floating point data formats
comprising: decoding means for decoding an instruction in response to a
first phase of a first clock pulse to begin the conversion of a floating
point number having a first kind of format and for providing signal when
said instruction is received; constant generating means for providing a
certain constant prior to the end of a second phase of said first clock
pulse in response to said first signal; latching means or latching said
floating point number in aid first kind of format and said certain
constant; and adder means for adding said certain constant to said floating
point number of said first kind of format to produce a result which is said
floating point number in a second kind of format.
Class: 364715030
IPC: G06F-007/38
4/5/2 (Item 2 from file: 25)
2048443 3030198
E/ Sticky bit predictor for floating-point multiplication
Inventors: Galbi David (US); Kohn Les (US)
Assignee: Intel Corp Assignee Codes: 42458 Document Type: UTILITY
Applic Applic Patent Issue
Number Date Number Date
--------- ------ ---------- ------
Patent: US 248740 880923 US 4928259 900522
Priority Applic: US 248740 880923
Abstract:
In a floating-point multiplication of two numbers in which a value of a
sticky bit is needed, each of two trailing zero encoders calculates the
number of trailing zeroes associated with its mantissa. The sum of the two
trailing zero counts determines the number of trailing zeroes in the
mantissa product. This sum is compared to a constant to determine the
sticky bit. Each encoder is comprised of a plurality of individual encoders
arranged in a plurality of rows for providing the trailing zero count.
Claim:
D R A W I N G
1. A circuit for predicting a sticky bit value when multiplying two
numbers comprising: a first trailing zero encoder for determining a number
of trailing zeros in a first operand mantissa; a second trailing zero
encoder for determining a number of trailing zeros in a second operand
mantissa; an adder coupled to receive outputs of said first and second
trailing zero encoders and providing a sum of said outputs to determine
total number of trailing zeros in both said operand mantissas; a comparing
means coupled to said adder for determining if said sum is greater than a
predetermined number, wherein determining said sticky bit value.
Class: 364745000
Cross Ref: 364757000
IPC: G06F-007/38
Cross Ref: G06F-007/52
4/5/3 (Item 3 from file: 25)
1935635 2922567
E/ MIXED-PRECISION FLOATING POINT OPERATIONS FROM A SINGLE INSTRUCTION
OPCODE
Inventors: IMEL MICHAEL T (US); LAI KONRAD (US); MYERS GLENFORD J (US);
STECK RANDY (US); VALERIO JAMES (US)
Assignee: INTEL CORP Assignee Codes: 42458 Document Type: UTILITY
Applic Applic Patent Issue
Number Date Number Date
--------- ------ ---------- ------
Patent: US 119547 871112 US 4823260 890418
Priority Applic: US 119547 871112
Abstract:
APPARATUS FOR PERFORMING MIXED PRECISION CALCULATIONS IN THE FLOATING
POINT UNIT OF A MICROPROCESSOR FROM A SINGLE INSTRUCTION OPCODE. 80-BIT
FLOATING-POINT REGISTERS (44) MAY BE SPECIFIED AS THE SOURCE OR DESTINATION
ADDRESS OF A FLOATING-POINT INSTRUCTION. WHEN THE ADDRESS RANGE OF THE
DESTINATION INDICATES (26) THAT A FLOATING POINT REGISTER IS ADDRESSED, THE
RESULT OF THAT OPERATION IS NOT ROUNDED TO THE PRECISION SPECIFIED BY THE
INSTRUCTION, BUT IS ROUNDED (58) TO EXTENDED 80-BIT PRECISION AND LOADED
INTO THE FLOATING POINT REGISTER (FP-44). WHEN THE ADDRESS RANGE OF THE
SOURCE INDICATES (26) THAT AN FP REGISTER IS ADDRESSED, THE DATA IS LOADED
FROM THE FP REGISTER IN EXTENDED PRECISION, REGARDLESS OF THE PRECISION
SPECIFIED BY THE INSTRUCTION. IN THIS WAY, REAL AND LONG-REAL OPERATIONS
CAN BE MADE TO USE EXTENDED PRECISION NUMBERS WITHOUT EXPLICITLY SPECIFYING
THAT IN THE OPCODE.
Claim:
D R A W I N G
1. IN A DATA PROCESSOR INCLUDING AN INSTRUCTION DECODER (12) AND A
FLOATING POINT UNIT (22) CONNECTED TOGETHER BY A MICROINSTRUCTION BUS (29)
WHICH CARRIES A CURRENT MICROINSTRUCTION GENERATED BY SAID DECODER IN THE
COURSE OF THE DECODING OF A MACROINSTRUCTION BY SAID DECODER, SAID
MACROINSTRUCTION INCLUDING A SOURCE ADDRESS FIELD, A DESTINATION ADDRESS
FIELD, AND AN OPCODE FIELD, SAID OPCODE FIELD INCLUDING FIRST MEANS (LL0,
LL1) SPECIFYING THE PRECISION OF ARITHMETIC OPERATIONS SPECIFIED BY SAID
MACROINSTRUCTION, THE IMPROVEMENT CHARACTERIZED BY: SAID MICROINSTRUCTION
GENERATED BY SAID INSTRUCTION DECODER (12) INCLUDING SECOND MEANS (OPCODE
1) FOR INDICATING THAT THE ADDRESS RANGE OF SAID SOURCE OR DESTINATION
ADDRESS IN SAID MACROINSTRUCTION INCLUDES THE ADDRESS OF A FLOATING POINT
REGISTER (44) IN SAID FLOATING POINT UNIT 22; AND, THIRD MEANS (73, 75)
RESPONSIVE TO SAID SECOND MEANS (OPCODE 1) FOR MODIFYING SAID FIRST MEANS
(LL0, LL1) TO SPECIFY EXTENDED PRECISION.
Class: 364200000
Cross Ref: 364745000; 364748000
IPC: G06F-007/48
4/5/4 (Item 4 from file: 25)
1922938 2913235
E/ STACK FRAME CACHE ON A MICROPROCESSOR CHIP
Inventors: HINTON GLENN (US); IMEL MICHAEL T (US); LAI KONRAD (US); MYERS
GLENFORD J (US); RICHES ROBERT (US)
Assignee: INTEL CORP Assignee Codes: 42458 Document Type: UTILITY
Applic Applic Patent Issue
Number Date Number Date
--------- ------ ---------- ------
Patent: US 863878 860516 US 4811208 890307
Priority Applic: US 863878 860516
Abstract:
A PLURALITY OF GLOBAL REGISTERS ARE PROVIDED ON THE MICROPROCESSOR CHIP.
ONE OF A GLOBAL REGISTERS IS A FRAME POINTER REGISTER CONTAINING THE
CURRENT FRAME POINTER, AND THE REMAINDER OF THE GLOBAL REGISTERS ARE
AVAILABLE TO A CURRENT PROCESS AS GENERAL REGISTERS. A PLURALITY OF
FLOATING POINT REGISTERS ARE ALSO PROVIDED FOR USE BY THE CURRENT PROCESS
IN EXECUTION OF FLOATING POINT ARITHMETIC OPERATIONS. A REGISTER SET POOL
MADE UP OF A PLURALITY OF REGISTER SETS IS PROVIDED, EACH REGISTER SET
BEING COMPRISED OF A NUMBER OF LOCAL REGISTERS. WHEN A CALL INSTRUCTION IS
DECODED, A REGISTER SET OF LOCAL REGISTERS FROM THE REGISTER SET POOL IS
ALLOCATED TO THE CALLED PROCEDURE, AND THE FRAME POINTER REGISTER IS
INITIALIZED. WHEN A RETURN INSTRUCTION IS DECODED, THE REGISTER SET IS
FREED FOR ALLOCATION TO ANOTHER PROCEDURE CALLED BY A SUBSEQUENT CALL
INSTRUCTION. IF THE REGISTER SET POOL IS DEPLETED A REGISTER SET ASSOCIATED
WITH A PREVIOUS PROCEDURE IS SAVED IN THE MAIN MEMORY, AND THAT REGISTER
SET IS ALLOCATED TO THE CURRENT PROCEDURE. THE LOCAL REGISTERS IN A
REGISTER SET ASSOCIATED WITH A PROCEDURE CONTAIN LINKAGE INFORMATION
INCLUDING A POINTER TO THE PREVIOUS FRAME AND AN INSTRUCTION POINTER, THUS
ENABLING MOST CALL AND RETURN INSTRUCTIONS TO EXECUTE WITHOUT NEEDING ANY
REFERENCES TO OFFCHIP MEMORY.
Claim:
D R A W I N G
1. A DATA PROCESSOR FABRICATED ON AN INTEGRATED CIRCUIT CHIP, SAID
DATA PROCESSOR INCLUDING AN INSTRUCTION EXECUTION UNIT (24), SAID DATA
PROCESSOR HAVING A MAIN MEMORY BUS (LOCAL BUS) FOR CONNECTING SAID DATA
PROCESSOR TO A MAIN MEMORY, SAID MAIN MEMORY BEING EXTERNAL TO SAID CHIP,
SAID MAIN MEMORY HAVING STORED THEREIN FIRST PROGRAM INSTRUCTIONS OF A
FIRST PROCESS AND PROGRAM INSTRUCTIONS OF A SECOND PROCESS, SAID FIRST
INSTRUCTIONS INCLUDING A CALL INSTRUCTION FOR CALLING SAID SECOND PROCESS,
SAID DATA PROCESSOR HAVING A REGISTER (STACK FRAME) CACHE (23), THE
IMPROVEMENT IN SAID DATA PROCESSOR COMPRISING: A PLURALITY (G0-G15) OF
GLOBAL REGISTERS (21) ON SAID INTEGRATED CIRCUIT CHIP, ONE (G15) OF SAID
GLOBAL REGISTERS BEING A FRAME POINTER REGISTER CONTAINING A CURRENT FRAME
POINTER WHICH POINTS TO A CURRENT FRAME CORRESPONDING TO A CURRENT PROCESS
RUNNING ON SAID PROCESSOR, AND THE REMAINDER OF SAID GLOBAL REGISTERS BEING
GENERAL REGISTERS AVAILABLE TO SAID CURRENT PROCESS; A REGISTER SET POOL IN
SAID REGISTER CACHE (23) ON SAID INTEGRATED CIRCUIT CHIP MADE UP OF A
PLURALITY OF REGISTER SETS, EACH REGISTER SET BEING COMPRISED OF A NUMBER
OF LOCAL REGISTERS; ADDRESS TRANSLATION MEANS (18, 24) CONNECTED TO SAID
REGISTER CACHE (23) FOR MAPPING SAID LOCAL REGISTERS ONTO CORRESPONDING
FRAMES IN THE ADDRESS SPACE OF SAID MAIN MEMORY EXTERNAL TO SAID CHIP; SAID
FRAME POINTER REGISTER (G15) INCLUDING A FRAME POINTER WHICH POINTS TO AN
EARLIER ALLOCATED REGISTER SET; SAID LOCAL REGISTERS OF EACH REGISTER SET
PROVIDING SPACE FOR STORING LINKAGE INFORMATION INCLUDING A PREVIOUS FRAME
POINTER (H6) WHICH CONTAINS THE ADDRESS OF A LOCATION IN SAID MAIN MEMORY
OF THE LAST PREVIOUSLY ACTIVATED FRAME AND A RETURN INSTRUCTION POINTER
(RIP) WHICH CONTAINS THE INSTRUCTION POINTER OF THE NEXT SEQUENTIAL
INSTRUCTION IN THE INSTRUCTION STREAM OF THE PROCESS THAT HAD CREATED THE
FRAME TO WHICH SAID REGISTER SET CORRESPONDS; A FIRST ONE OF SAID REGISTER
SETS BEING ALLOCATED TO SAID FIRST PROCESS; AN INTERNAL BUS IN SAID
PROCESSOR CONNECTING TOGETHER SAID REGISTER CACHE (23), SAID GLOBAL
REGISTERS (21) AND SAID INSTRUCTION EXECUTION UNIT (24); SAID GLOBAL
REGISTERS (21) AND SAID LOCAL REGISTERS (23) BEING ADDRESSABLE OVER SAID
INTERNAL BUS BY MICROINSTRUCTIONS EXECUTED BY SAID INSTRUCTION EXECUTION
UNIT (24) IN SAID DATA PROCESSOR; AN INSTRUCTION DECODER (12) CONNECTED TO
SAID INSTRUCTION EXECUTION UNIT (24); AND, CONTROL MEANS (14) IN SAID
PROCESSOR, RESPONSIVE TO SAID INSTRUCTION DECODER (12) AND ACTIVATED UPON
THE DECODING BY SAID INSTRUCTION DECODER (12) OF SAID CALL INSTRUCTION OF
SAID FIRST PROCESS, FOR ALLOCATING TO SAID SECOND PROCESS, A SECOND
REGISTER SET OF LOCAL REGISTERS FROM SAID REGISTER SET POOL IN SAID
REGISTER CACHE (23) AND FOR PLACING IN SAID FRAME POINTER REGISTER (G15) A
CURRENT FRAME POINTER WHICH POINTS TO SAID SECOND REGISTER SET, SAID
CONTROL MEANS (14) INCLUDING MEANS FOR TRANSFERRING, OVER SAID MAIN MEMORY
BUS (LOCAL BUS) TO SAID MAIN MEMORY, THE CONTENTS OF AN EARLIER ALLOCATED
REGISTER SET PREVIOUSLY ALLOCATED TO AN EARLIER ACTIVATED PROCESS, AND FOR
REALLOCATING SAID EARLIER ALLOCATED REGISTER SET TO SAID CURRENT PROCESS,
BY PLACING IN SAID FRAME POINTER REGISTER (G15) THE FRAME POINTER WHICH
POINTS TO SAID EARLIER ALLOCATED REGISTER SET.
Class: 364200000
IPC: G06F-012/08
4/5/5 (Item 5 from file: 25)
1560501 2447039
E/ FRACTION BUS FOR USE IN A NUMERIC DATA PROCESSOR
Inventors: NAVE RAFI (IL); PALMER JOHN (US); RAVENEL BRUCE (US)
Assignee: INTEL CORP Assignee Codes: 42458 Document Type: UTILITY
Applic Applic Patent Issue
Number Date Number Date
--------- ------ ---------- ------
Patent: US 341703 820122 US 4484259 841120
(Cited in 009 later patents)
Division of: US 120995 800213 US 4338675
Priority Applic: US 341703 820122
US 120995 800213
Abstract:
A FLOATING POINT, INTEGRATED, ARITHMETIC CIRCUIT IS ORGANIZED AROUND A
FILE FORMAT HAVING A FLOATING POINT NUMERIC DOMAIN EXCEEDING THAT OF ANY
SINGLE OR DOUBLE PRECISION FLOATING POINT NUMBERS, LONG OR SHORT INTEGER
WORDS OF BCD DATA UPON WHICH IT MUST OPERATE. AS A RESULT THE CIRCUIT HAS A
GREATER RELIABILITY, RANGE AND PRECISION THAN EVER PREVIOUSLY ACHIEVED
WITHOUT ENTAILING ADDITIONAL CIRCUIT COMPLEXITY. RELIABILITY IS FURTHER
ENHANCED BY A SYSTEMATIC THREE BIT ROUNDING FIELD, AND BY INCLUDING MEANS
FOR DETECTING EVERY ERROR OR EXCEPTION CONDITION WITH AN OPTIONAL EXPECTED
RESPONSE PROVIDED THERETO BY HARDWARE. AS A RESULT OF SUCH ORGANIZATION, AN
UNEXPECTED INCREASE OF CAPACITY IS ACHIEVED WHEREIN TRANSCENDENTAL
FUNCTIONS CAN BE COMPUTED TOTALLY IN HARDWARE, AND WHEREBY MIXED MODE
ARITHMETIC CAN BE IMPLEMENTED WITHOUT DIFFICULTY. THE NUMERIC PROCESSOR
ALSO INCLUDES A PROGRAMMABLE SHIFTER CAPABLE OF ARBITRARY NUMBERS OF BIT
AND BYTE SHIFTS IN A SINGLE CLOCK CYCLE, AS WELL AS AN ARITHMETIC UNIT
CAPABLE OF IMPLEMENTING MULTIPLICATION, DIVISION, MODULO REDUCTION AND
SQUARE ROOTS DIRECTLY IN HARDWARE.
Claim:
D R A W I N G S
1. AN IMPROVEMENT IN A NUMERIC PROCESSOR HAVING A FRACTION BUS, SAID
PROCESSOR FOR PERFORMING ARITHMETIC CALCULATIONS COMPRISING: AN ADDER
HAVING A FIRST INPUT COUPLED TO SAID FRACTION BUS; SUM MEANS FOR STORING
AND SHIFTING NUMERIC QUANTITIES, THE INPUT OF SAID SUM MEANS COUPLED TO AN
OUTPUT OF SAID ADDER, THE OUTPUT OF SAID SUM MEANS COUPLED TO SAID FRACTION
BUS; A MULTIPLEXED REGISTER HAVING ITS OUTPUT COUPLED TO A SECOND INPUT OF
SAID ADDER, THE INPUT OF SAID MULTIPLEXED REGISTER COUPLED TO SAID FRACTION
BUS; A SKIP SHIFTER HAVING A FIRST OUTPUT COUPLED TO A THIRD INPUT OF SAID
ADDER; AND CONTROL MEANS COUPLED TO SAID SUM MEANS AND MULTIPLEXED REGISTER
TO SELECTIVELY CONTROL SAID SUM MEANS AND SAID MULTIPLEXED REGISTER
DEPENDING ON THE ARITHMETIC OPERATION TO BE PERFORMED, A SECOND OUTPUT OF
SAID SKIP SHIFTER BEING COUPLED TO SAID CONTROL MEANS TO SELECTIVELY
PROVIDE CONTROL INFORMATION THERETO, WHEREBY MULTIPLICATION OPERATIONS MAY
BE SELECTIVELY PERFORMED.
Class: 364754000
Cross Ref: 364736000; 364748000; 364761000
IPC: G06F-007/44
4/5/6 (Item 6 from file: 25)
1402965 2223135
E/ NUMERIC DATA PROCESSOR
Inventors: NAVE RAFI (IL); PALMER JOHN F (US); RAVENEL BRUCE W (US)
Assignee: INTEL CORP Assignee Codes: 42458 Document Type: UTILITY
Applic Applic Patent Issue
Number Date Number Date
--------- ------ ---------- ------
Patent: US 120995 800213 US 4338675 820706
(Cited in 020 later patents)
Priority Applic: US 120995 800213
Abstract:
A FLOATING POINT, INTEGRATED, ARITHMETIC CIRCUIT IS ORGANIZED AROUND A
FILE FORMAT HAVING A FLOATING POINT NUMERIC DOMAIN EXCEEDING THAT OF ANY
SINGLE OR DOUBLE PRECISION FLOATING POINT NUMBERS, LONG OR SHORT INTEGER
WORDS OR BCD DATA UPON WHICH IT MUST OPERATE. AS A RESULT THE CIRCUIT HAS A
GREATER RELIABILITY, RANGE AND PRECISION THAN EVER PREVIOUSLY ACHIEVED
WITHOUT ENTAILING ADDITIONAL CIRCUIT COMPLEXITY. RELIABILITY IS FURTHER
ENHANCED BY A SYSTEMATIC THREE BIT ROUNDING FIELD, AND BY INCLUDING MEANS
FOR DETECTING EVERY ERROR OR EXCEPTION CONDITION WITH AN OPTIONAL EXPECTED
RESPONSE PROVIDED THERETO BY HARDWARE. AS A RESULT OF SUCH ORGANIZATION, AN
UNEXPECTED INCREASE OF CAPACITY IS ACHIEVED WHEREIN TRANSCENDENTAL
FUNCTIONS CAN BE COMPUTED TOTALLY IN HARDWARE, AND WHEREBY MIXED MODE
ARITHMETIC CAN BE IMPLEMENTED WITHOUT DIFFICULTY. THE NUMERIC PROCESSOR
ALSO INCLUDES A PROGRAMMABLE SHIFTER CAPABLE OF ARBITRARY NUMBERS OF BIT
AND BYTE SHIFTS IN A SINGLE CLOCK CYCLE, AS WELL AS AN ARITHMETIC UNIT
CAPABLE OF IMPLEMENTING MULTIPLICATION, DIVISION, MODULO REDUCTION AND
SQUARE ROOTS DIRECTLY IN HARDWARE.
Claim:
1. AN IMPROVED IN A NUMERIC DATA PROCESSOR FOR PERFORMING CALCULATIONS ON
A PLURALITY OF DATA FORMATS REPRESENTABLE BY A FRACTION AND EXPONENT
REPRESENTATION COMPRISING: FIRST MEANS FOR CONVERTING SAID PLURALITY OF
DATA FORMATS TO A FILE FORMAT HAVING A FRACTION AND EXPONENT REPRESENTATION
WHEREIN SAID FILE FORMAT HAS A NUMERIC FRACTION AND EXPONENT DOMAIN GREATER
THAN ANY OF SAID PLURALITY OF DATA FORMATS; A FRACTION AND EXPONENT BUS
COUPLED TO SAID FIRST MEANS; A STACK OF REGISTERS CONFIGURED TO STORE
NUMERIC INFORMATION IN SAID FILE FORMAT, SAID STACK COUPLED TO SAID
EXPONENT AND FRACTION BUS; AN ARITHMETIC UNIT TO PERFORM ARITHMETIC
OPERATIONS ON SAID INFORMATION IN SAID FILE FORMAT, SAID ARITHMETIC UNIT
BEING COUPLED TO SAID FRACTION BUS; AND MEANS FOR ROUNDING SAID NUMERIC
INFORMATION IN A SELECTED ONE OF A PLURALITY OF MODES,
D R A W I N GES A THREE BIT REGISTER
WHEREIN SAID MEANS FOR ROUNDING INCLUDES A THREE BIT REGISTER FOR
STORING A GUARD, ROUND AND STICKY BIT CORRESPONDING TO A NUMERIC QUANTITY,
SAID STICKY BIT BEING THE OR-FUNCTION OF ALL RIGHT BITS FROM SAID NUMERIC
QUANTITY BEYOND THE BIT LOCATION OF SAID GUARD AND ROUND BITS.
Class: 364748000
Cross Ref: 364200000; 364224000; 364230000; 364230400; 364232800; 364240000
; 364244000; 364244300; 364247000; 364247800; 364258000; 364258100;
364258200; 364258300; 364258400; 364259000; 364259500; 364259700;
364260400; 364260900; 364263000; 364263100; 364264000; 364264200;
364265000; 364265400; 364266400; 364271000; 364271200; 364715080;
364737000; 364745000
IPC: G06F-007/48
Cross Ref: G06F-011/00; G06F-009/00
?\021
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