1991 - an exciting year for announcements - from comp.arch

[David G. Hough on validgh]

From: mslateracup.portal.com (Michael Z Slater)
Subject: New Microprocessors Expected in 1991
Date: 29 Dec 90 22:05:24 GMT

I'm working up a list of all the new high-performance microprocessors 
expected in 1991. I'd appreciate any additions to the list or details anyone 
can fill in. I'm especially interested in anticipated introduction and 
sampling dates, and projected clock rates and performance. I'll post an 
updated version after I've collected responses. Here's the list so far:

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LSI Logic's "Lightning" SPARC processor. Five-chip superscalar 
implementation, dispatches up to four instructions per clock. Uses out-of-
order instruction execution, speculative execution, and register relabeling.

Texas Instruments' "Viking" SPARC processor. Superscalar and superpipelined, 
dispatches up to three instructions per clock. On-chip caches approximately 
16 Kbytes each for instructions and data.

Cypress/ROSS Technology's "Pinnacle" SPARC processor. Superscalar, dispatches 
up to two instructions per clock cycle. On chip cache approximately 16 
Kbytes, external MMU and controller for second-level cache.

SPARC processors combining existing integer and floating-point units from 
Fujitsu and LSI Logic.

MIPS' R4000. Superpipelined processor, on-chip clock doubler. On-chip 
instruction and data caches 8 Kbytes each, controller for external second-
level cache. Implements MIPS-2 architecture extensions.

Motorola's 88110, a superscalar implementation of the 88000 architecture with 
on-chip instruction and data caches of 8K each, 80-bit floating-point 
support, separate floating-point and integer registers, graphics execution 
unit.

Motorola's 68EC040, a low-cost variant of the 68040 with no floating-point or 
memory management units and instruction and data caches of 2K each instead of 
4K each.

Intel's "N11," the next-generation 860-family processor. Includes larger 
caches with support for multiprocessor cache coherency, plus support for MPAX 
loop- level parallelism scheme.

Intel's "P23," a low-cost version of the 486 that the press has called the 
486SX. A 486 without the floating-point unit, and possibly with a smaller 
cache.

Hitachi's Precision Architecture processor, the first implementation of 
Hewlett- Packard's RISC architecture to be offered as a chip-level product.

Samsung's Clipper implementation for embedded control. Likely to include 
modest on-chip caches.

VLSI Technology's next-generation Acorn RISC Machine (ARM). Will include 
instruction set extensions and on-chip cache.

National Semiconductor's "Swordfish," a superscalar processor loosely based 
on the 32000 architecture but not binary compatible. Designed for embedded 
control applications, includes on-chip peripherals.

Inmos' "H1" Transputer, a new generation of Transputer with higher- 
performance "links" and a faster processor core.

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I'll send a free copy of the first 1991 issue of Microprocessor Report, which 
will include an embellished version of this list, to anyone who contributes 
to it.

Michael Slater, Microprocessor Report        mslateracup.portal.com
874 Gravenstein Hwy. So., Suite 14, Sebastopol, CA 95472
707/823-4004   fax: 707/823-0504