extracts from 4 Dec 91 Microprocessor Report

[David G. Hough on validgh]

The PowerPC will differ from the RS/6000 - some instructions have been
deleted, others added.   Among the latter are single-precision floating point.
Not clear whether this was public or rumor.

A court in Texas denied Intel's request for a preliminary injunction against
Cyrix 387 replacement.   
Trials on various issues will start in Jan, Aug, and Dec 92.

P5 Rumor:  P5 apparently does not include new incompatible fp registers
and instructions.  Performance is achieved compatibly somehow.

P5 Public:  At the Microprocessor Forum, in a debate with Hennessy,
Patrick Gelsinger of Intel said 
	P5 floating-point performance will exceed that of R4000
(presumably for both at 50 MHz shipping some time in 92)
	P5 is almost done, and a group is working on the next
0.6 micron implementation
	686 is "well under way"
	the team for the next product after (P6 == 686 ?) is "deployed"
	The inherent advantages of RISC over x86 are fixed length instructions
and large register sets, and these x86 disadvantages are succumbing to the same
implementation techniques used in advanced RISC designs
	"Some of the design teams working on the x86 architecture don't
even work at Intel!" - not clear whether this just referred to the IBM-Intel
joint development effort or something else.