[Cfp-interest] Fw: ISO/IEC JTC 1/SC 22/WG 14 New documents available on ISOTC eCommittee - short float
Ian McIntosh
ianm at ca.ibm.com
Mon Mar 14 12:59:46 PDT 2016
I think adding short float is a good idea, as long as it doesn't interfere
with _Float16 where that's available and as long as it's either optional or
can be implemented as binary32 where there's no hardware support for
anything smaller (as section 4.1 allows).
ARM has 2 __fp16 types. One is binary16. One is not, having a slightly
bigger exponent range instead of Infinities and NaNs (like the CELL SPUs).
Nvidia half is the same as binary16. I think half2 is a vector of 2 half
s, getting 2x speed.
OpenEXR HALF is almost the same as binary16, except only supporting the
default rounding mode.
In section 3.1 "_Float16 . . . The specification is general in that it can
handle a wide range of lengths. However, it only permits an exact size."
That's true, but _Float16x allows any other representation with (1) IEEE
semantics including Infinities and NaNs, (2) at least the exponent range of
_Float16, and (3) at least the precision of _Float16. That might handle
some of the other "half" precision variants listed in section 2.3. It
might handle TI's 20 bit. It would not handle OpenGL's 10 or 11 bit (or
14, which I was unable to find in the OpenGL spec) and maybe not TI's 20
bit.
In section 2.1, Adobe also has 24 bit floating-point, not just 16.
In section 5.4, should promotion be to float except where float would be
promoted to double? On many CPUs, "float f; short float sf; . . . f+sf"
would be faster when evaluated as a float than as a double. Some CPUs/GPUs
process half or half2 precision up to twice as fast as single precision, so
is promotion necessary on them?
- Ian McIntosh IBM Canada Lab Compiler Back End Support
and Development
From: "Rajan Bhakta" <rbhakta at us.ibm.com>
To: cfp-interest at oakapple.net
Date: 2016-03-14 12:44 PM
Subject: [Cfp-interest] Fw: ISO/IEC JTC 1/SC 22/WG 14 New documents
available on ISOTC eCommittee
Sent by: cfp-interest-bounces at oakapple.net
FYI, this new document is being brought up for the next WG14 meeting by
another group.
One point I want to make is in 3.1 the _Float16x (which we do *not* specify
in Part 3 of the TS) may be appropriate in some cases, but the
"readability" argument and non-IEEE argument is still there.
Regards,
Rajan Bhakta
z/OS XL C/C++ Compiler Technical Architect
ISO C Standards Representative for Canada
C Compiler Development
Contact: rbhakta at us.ibm.com, Rajan Bhakta/Houston/IBM
----- Forwarded by Rajan Bhakta/Houston/IBM on 03/14/2016 10:08 AM -----
From: Daniel Plakosh <livelinkisotc at iso.org>
To: Rajan Bhakta/Houston/IBM at IBMUS
Date: 03/14/2016 09:18 AM
Subject: ISO/IEC JTC 1/SC 22/WG 14 New documents available on ISOTC
eCommittee
Dear member,
Please note that the following new documents have been posted
on the ISO/IEC JTC 1/SC 22/WG 14 eCommittee:
N Title (Description) Exp. Due Version
Number Action Date Date
2016 Adding Fundamental INFO None 2016-03-14
Type for Short
Float
2011 ISO/IEC TS 17961 INFO None 2016-03-14
with TC1
Incorporated
Download all documents as ZIP : ZIP-File
Access to ISO/IEC JTC 1/SC 22/WG 14 : Committee Homepage
Please inform us if you have any difficulty accessing the above documents.
For help with technical
problems please contact helpdesk at iso.org .
Best regards
dplakosh at cert.org
[attachment
"ISO-IECJTC1-SC22-WG14_N2016_Adding_Fundamental_Type_for_Shor.pdf" deleted
by Ian McIntosh/Toronto/IBM]
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