[Cfp-interest] FP_EXCEPTIONAL and subexceptions

Ian McIntosh ianm at ca.ibm.com
Wed May 14 18:43:35 PDT 2014


On PowerPC, to detect all exceptions that occurred in a block of code would
involve something like:
      Copy the FPSCR (Floating-Point Status and Control Register) to a
      floating point/vector register (serializing on some CPU models).
      Make a copy of that with all status bits (the sticky bits that report
      an exception happened) cleared so changes can be detected,
      and with all exception-signaling-enabled control bits (the bits that
      say to create an interrupt) cleared so a signal handler won't be
      called.
      Copy that to the FPSCR (serializing on most CPU models).
      Execute the block of code.  Any exceptions that occur will be
      recorded in the status bits but will not call a signal handler.
      Copy the FPSCR to another floating point/vector register (serializing
      on some CPU models).
      Extract all the status bits.
      Probably OR all the status bits into the FPSCR copy saved in step 1.
      Write the saved FPSCR (probably with the new status bits ORed in)
      back to the FPSCR (serializing on most CPU models),
      restoring the original exception-signaling-enabled control bits and
      the original or original+new status bits.
      Compare the extracted status bits to zero.
      If nonzero, execute the alternate handling code.

To detect one or more exceptions the programmer specifies that occurred in
a block of code would involve something like:
      Copy the FPSCR (Floating-Point Status and Control Register) to a
      floating point/vector register (serializing on some CPU models).
      Make a copy of that with the specified status bit(s) (the sticky bits
      that report an exception happened) cleared so changes can be
      detected,
      and with the specified exception-signaling-enabled flags (the bits
      that say to create an interrupt) cleared so a signal handler won't be
      called.
      Copy that to the FPSCR (serializing on most CPU models).
      Execute the block of code.  Any exceptions that occur will be
      recorded in the status bits but will not call a signal handler.
      Copy the FPSCR to another floating point/vector register (serializing
      on some CPU models).
      Extract the specified status bits.
      Probably OR the specified status bit(s) into the FPSCR copy saved in
      step 1.
      Write the saved FPSCR (probably with the new status bit(s) ORed in)
      back to the FPSCR (serializing on most CPU models).
      Compare the extracted status bit(s) to zero.
      If nonzero, execute the alternate handling code.

Not much difference.

With the assumption that no exception-signaling-enabled flags are set, and
that only one or a few exceptions need to be detected, and that the
original status bits don't need to be preserved, that can be simplified:
      Clear the individual status bits for the exception(s) that need to be
      detected (serializing on most CPU models).
      Execute the block of code.  Any exceptions that occur will be
      recorded in the status bits.
      Copy the FPSCR to a floating point/vector register (serializing on
      some CPU models).
      Extract the specified status bit(s).
      Compare the extracted status bit(s) to zero.
      If nonzero, execute the alternate handling code.

That's still noticeably slower than a compare and conditional branch, but
getting reasonable for at least some uses.

What would be needed on other architectures?

- Ian McIntosh          IBM Canada Lab         Compiler Back End Support
and Development



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  |David Hough CFP <pcfp at oakapple.net>                                                                                                        |
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  |cfp-interest at ucbtest.org,                                                                                                                  |
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  |2014-05-14 07:51 PM                                                                                                                        |
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  |[Cfp-interest] FP_EXCEPTIONAL and subexceptions                                                                                            |
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  |cfp-interest-bounces at oakapple.net                                                                                                          |
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There's a real problem with defining FP_EXCEPTIONAL without a list
of exceptions or subexceptions of interest.     In that case it has
to return a complete list of exceptions and subexceptions, whether you're
interested in them or not.     In general, executing code and determining
which subexceptions arose is going to be expensive and so you wouldn't
want to do that unless you cared.

Remember one of the goals here is that if the exception of interest does
NOT arise, then the typical use case is that the just-computed test
expression is actually the result you want.    So it needs to be ready
for use and efficient as well since it gets executed every time, unlike
the special case code for exceptions of interest.

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